ZHCSF48D March 2016  – May 2017 ISO7740 , ISO7741 , ISO7742


  1. 特性
  2. 应用范围
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Power Rating
    6. 6.6 Insulation Specifications
    7. 6.7 Safety-Related Certifications
    8. 6.8 Safety Limiting Values
    9. 6.9 Electrical Characteristics—5-V Supply
    10. 6.10Supply Current Characteristics—5-V Supply
    11. 6.11Electrical Characteristics—3.3-V Supply
    12. 6.12Supply Current Characteristics—3.3-V Supply
    13. 6.13Electrical Characteristics—2.5-V Supply
    14. 6.14Supply Current Characteristics—2.5-V Supply
    15. 6.15Switching Characteristics—5-V Supply
    16. 6.16Switching Characteristics—3.3-V Supply
    17. 6.17Switching Characteristics—2.5-V Supply
    18. 6.18Insulation Characteristics Curves
    19. 6.19Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1Electromagnetic Compatibility (EMC) Considerations
    4. 8.4Device Functional Modes
      1. 8.4.1Device I/O Schematics
  9. Application and Implementation
    1. 9.1Application Information
    2. 9.2Typical Application
      1. 9.2.1Design Requirements
      2. 9.2.2Detailed Design Procedure
      3. 9.2.3Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1Layout Guidelines
      1. 11.1.1PCB Material
    2. 11.2Layout Example
  12. 12器件和文档支持
    1. 12.1文档支持
      1. 12.1.1相关文档
    2. 12.2相关链接
    3. 12.3接收文档更新通知
    4. 12.4社区资源
    5. 12.5商标
    6. 12.6静电放电警告
    7. 12.7Glossary
  13. 13机械、封装和可订购信息


Layout Guidelines

A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 27). Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer.

  • Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link.
  • Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow.
  • Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pF/inch2.
  • Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias.

If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly.

For detailed layout recommendations, refer to the Digital Isolator Design Guide (SLLA284).

PCB Material

For digital circuit boards operating below 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit boards. This PCB is preferred over cheaper alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and self-extinguishing flammability-characteristics.

Layout Example

ISO7740 ISO7741 ISO7742 Layout_sllsei8.gif Figure 27. Layout Example Schematic