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LVDS、M-LVDS 和 PECL IC

DS91D180

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100MHz M-LVDS 线路驱动器/接收器组合

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数据表

DS91D180

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数据表 立即订购

产品详情

Function Transceiver Protocols M-LVDS Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 200 Input signal LVTTL, M-LVDS Output signal LVTTL, M-LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Transceiver Protocols M-LVDS Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 200 Input signal LVTTL, M-LVDS Output signal LVTTL, M-LVDS Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 14 51.9 mm² 8.65 x 6
  • DC to 100+ MHz / 200+ Mbps Low Power, Low EMI Operation
  • Optimal for ATCA, uTCA Clock Distribution Networks
  • Meets or Exceeds TIA/EIA-899 M-LVDS Standard
  • Wide Input Common Mode Voltage for Increased Noise Immunity
  • DS91D180 has Type 1 Receiver Input
  • DS91C180 has Type 2 Receiver Input for Fail-Safe Functionality
  • Industrial Temperature Range
  • Space Saving SOIC-14 Package (JEDEC MS-012)

All trademarks are the property of their respective owners.

  • DC to 100+ MHz / 200+ Mbps Low Power, Low EMI Operation
  • Optimal for ATCA, uTCA Clock Distribution Networks
  • Meets or Exceeds TIA/EIA-899 M-LVDS Standard
  • Wide Input Common Mode Voltage for Increased Noise Immunity
  • DS91D180 has Type 1 Receiver Input
  • DS91C180 has Type 2 Receiver Input for Fail-Safe Functionality
  • Industrial Temperature Range
  • Space Saving SOIC-14 Package (JEDEC MS-012)

All trademarks are the property of their respective owners.

The DS91D180 and DS91C180 are 100 MHz M-LVDS (Multipoint Low Voltage Differential Signaling) line driver/receiver pairs designed for applications that utilize multipoint networks (e.g. clock distribution in ATCA and uTCA based systems). M-LVDS is a bus interface standard (TIA/EIA-899) optimized for multidrop networks. Controlled edge rates, tight input receiver thresholds and increased drive strength are sone of the key enhancments that make M-LVDS devices an ideal choice for distributing signals via multipoint networks.

The DS91D180/DS91C180 driver input accepts LVTTL/LVCMOS signals and converts them to differential M-LVDS signal levels. The DS91D180/DS91C180 receiver accepts low voltage differential signals (LVDS, B-LVDS, M-LVDS, LV-PECL and CML) and converts them to 3V LVCMOS signals. The DS91D180 device has a M-LVDS type 1 receiver input with no offset.The DS91C180 device has a type 2 receiver input which enable failsafe functionality.

The DS91D180 and DS91C180 are 100 MHz M-LVDS (Multipoint Low Voltage Differential Signaling) line driver/receiver pairs designed for applications that utilize multipoint networks (e.g. clock distribution in ATCA and uTCA based systems). M-LVDS is a bus interface standard (TIA/EIA-899) optimized for multidrop networks. Controlled edge rates, tight input receiver thresholds and increased drive strength are sone of the key enhancments that make M-LVDS devices an ideal choice for distributing signals via multipoint networks.

The DS91D180/DS91C180 driver input accepts LVTTL/LVCMOS signals and converts them to differential M-LVDS signal levels. The DS91D180/DS91C180 receiver accepts low voltage differential signals (LVDS, B-LVDS, M-LVDS, LV-PECL and CML) and converts them to 3V LVCMOS signals. The DS91D180 device has a M-LVDS type 1 receiver input with no offset.The DS91C180 device has a type 2 receiver input which enable failsafe functionality.
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类型 标题 下载最新的英语版本 日期
* 数据表 DS91D180/DS91C180 100 MHz M-LVDS Line Driver/Receiver Pair 数据表 (Rev. M) 2013年 4月 18日
应用简报 How Far, How Fast Can You Operate MLVDS? 2018年 8月 6日
应用手册 Designing an ATCA Compliant M-LVDS Clock Distribution Network (Rev. B) 2013年 4月 26日
应用手册 Introduction to M-LVDS (TIA/EIA-899) (Rev. A) 2013年 1月 3日
应用手册 Designing an ATCA Compliant M-LVDS Clock Distribution Network (cn) 2007年 11月 20日

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包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
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  • 封装厂地点

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