SNLS570 August 2017 DS90UB954-Q1

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 AC Electrical Characteristics
    7. 6.7 AC Electrical Characteristics CSI-2
    8. 6.8 Recommended Timing for the Serial Control Bus
    9. 6.9 Timing Diagrams
    10. 6.10Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
      1. 7.1.1Functional Description
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
    4. 7.4Device Functional Modes
      1. 7.4.1 CSI-2 Mode
      2. 7.4.2 RAW Mode
      3. 7.4.3 RX MODE Pin
      4. 7.4.4 REFCLK
      5. 7.4.5 Crystal Recommendations
      6. 7.4.6 Receiver Port Control
        1. 7.4.6.1Video Stream Forwarding
      7. 7.4.7 LOCK and PASS Status
      8. 7.4.8 Input Jitter Tolerance
      9. 7.4.9 Adaptive Equalizer
        1. 7.4.9.1Adaptive Equalizer Algorithm
        2. 7.4.9.2AEQ Settings
          1. 7.4.9.2.1AEQ Start-Up and Initialization
          2. 7.4.9.2.2AEQ Range
          3. 7.4.9.2.3AEQ Timing
          4. 7.4.9.2.4AEQ Threshold
      10. 7.4.10Channel Monitor Loop-Through Output Driver (CMLOUT)
        1. 7.4.10.1Code Example for CMLOUT FPD-Link III RX Port 0:
      11. 7.4.11RX Port Status
        1. 7.4.11.1RX Parity Status
        2. 7.4.11.2FPD-Link Decoder Status
        3. 7.4.11.3RX Port Input Signal Detection
        4. 7.4.11.4Line Counter
        5. 7.4.11.5Line Length
      12. 7.4.12Sensor Status
      13. 7.4.13GPIO Support
        1. 7.4.13.1GPIO Input Control and Status
        2. 7.4.13.2GPIO Output Pin Control
        3. 7.4.13.3Forward Channel GPIO
        4. 7.4.13.4Back Channel GPIO
        5. 7.4.13.5Other GPIO Pin Controls
      14. 7.4.14Line Valid and Frame Valid Indicators
      15. 7.4.15CSI-2 Protocol Layer
      16. 7.4.16CSI-2 Short Packet
      17. 7.4.17CSI-2 Long Packet
      18. 7.4.18CSI-2 Data Type Identifier
      19. 7.4.19Virtual Channel and Context
      20. 7.4.20CSI-2 Input Mode Virtual Channel Mapping
        1. 7.4.20.1Example 1
        2. 7.4.20.2Example 2:
      21. 7.4.21CSI-2 Transmitter Frequency
      22. 7.4.22 CSI-2 Replicate Mode
      23. 7.4.23 CSI-2 Transmitter Output Control
      24. 7.4.24CSI-2 Transmitter Status
      25. 7.4.25Video Buffers
      26. 7.4.26CSI-2 Line Count and Line Length
      27. 7.4.27FrameSync Operation
        1. 7.4.27.1External FrameSync Control
        2. 7.4.27.2Internally Generated FrameSync
          1. 7.4.27.2.1Code Example for Internally Generated FrameSync
      28. 7.4.28CSI-2 Forwarding
        1. 7.4.28.1Best-Effort Round Robin CSI-2 Forwarding
        2. 7.4.28.2Synchronized Forwarding
        3. 7.4.28.3Basic Synchronized Forwarding
          1. 7.4.28.3.1Code Example for Basic Synchronized Forwarding
        4. 7.4.28.4Line-Interleave Forwarding
          1. 7.4.28.4.1Code Example for Line-Interleave Forwarding
        5. 7.4.28.5Line-Concatenated Forwarding
          1. 7.4.28.5.1Code Example for Line-Concatenate Forwarding
    5. 7.5Programming
      1. 7.5.1 Serial Control Bus and Bidirectional Control Channel
        1. 7.5.1.1Bidirectional Control
        2. 7.5.1.2Device Address
        3. 7.5.1.3Basic I2C Serial Bus Operation
      2. 7.5.2 I2C Slave Operation
      3. 7.5.3 Remote Slave Operation
      4. 7.5.4 Remote Slave Addressing
      5. 7.5.5 Broadcast Write to Remote Slave Devices
        1. 7.5.5.1Code Example for Broadcast Write
      6. 7.5.6 I2C Master Proxy
      7. 7.5.7 I2C Master Proxy Timing
        1. 7.5.7.1Code Example for Configuring Fast Mode Plus I2C Operation
      8. 7.5.8 Interrupt Support
        1. 7.5.8.1Code Example to Enable Interrupts
        2. 7.5.8.2FPD-Link III Receive Port Interrupts
          1. 7.5.8.2.1Interrupts on Forward Channel GPIO
          2. 7.5.8.2.2Interrupts on Change in Sensor Status
        3. 7.5.8.3Code Example to Readback Interrupts
        4. 7.5.8.4CSI-2 Transmit Port Interrupts
      9. 7.5.9 Error Handling
        1. 7.5.9.1Receive Frame Threshold
        2. 7.5.9.2Port PASS Control
      10. 7.5.10Timestamp - Video Skew Detection
      11. 7.5.11Pattern Generation
        1. 7.5.11.1Reference Color Bar Pattern
        2. 7.5.11.2Fixed Color Patterns
        3. 7.5.11.3Packet Generator Programming
          1. 7.5.11.3.1Determining Color Bar Size
        4. 7.5.11.4Code Example for Pattern Generator
      12. 7.5.12FPD-Link BIST Mode
        1. 7.5.12.1BIST Operation Through BISTEN Pin
        2. 7.5.12.2BIST Operation Through Register Control
    6. 7.6Register Maps
      1. 7.6.1  I2C Device ID Register
      2. 7.6.2  Reset Register
      3. 7.6.3  General Configuration Register
      4. 7.6.4  Revision/Mask ID Register
      5. 7.6.5  DEVICE_STS Register
      6. 7.6.6  PAR_ERR_THOLD_ HI Register
      7. 7.6.7  PAR_ERR_THOLD_LO Register
      8. 7.6.8  BCC Watchdog Control Register
      9. 7.6.9  I2C Control 1 Register
      10. 7.6.10 I2C Control 2 Register
      11. 7.6.11 SCL High Time Register
      12. 7.6.12 SCL Low Time Register
      13. 7.6.13 RX_PORT_CTL Register
      14. 7.6.14 IO_CTL Register
      15. 7.6.15 GPIO_PIN_STS Register
      16. 7.6.16 GPIO_INPUT_CTL Register
      17. 7.6.17 GPIO0_PIN_CTL Register
      18. 7.6.18 GPIO1_PIN_CTL Register
      19. 7.6.19 GPIO2_PIN_CTL Register
      20. 7.6.20 GPIO3_PIN_CTL Register
      21. 7.6.21 GPIO4_PIN_CTL Register
      22. 7.6.22 GPIO5_PIN_CTL Register
      23. 7.6.23 GPIO6_PIN_CTL Register
      24. 7.6.24 RESERVED Register
      25. 7.6.25 FS_CTL Register
      26. 7.6.26 FS_HIGH_TIME_1 Register
      27. 7.6.27 FS_HIGH_TIME_0 Register
      28. 7.6.28 FS_LOW_TIME_1 Register
      29. 7.6.29 FS_LOW_TIME_0 Register
      30. 7.6.30 MAX_FRM_HI Register
      31. 7.6.31 MAX_FRM_LO Register
      32. 7.6.32 CSI_PLL_CTL Register
      33. 7.6.33 FWD_CTL1 Register
      34. 7.6.34 FWD_CTL2 Register
      35. 7.6.35 FWD_STS Register
      36. 7.6.36 INTERRUPT_CTL Register
      37. 7.6.37 INTERRUPT_STS Register
      38. 7.6.38 TS_CONFIG Register
      39. 7.6.39 TS_CONTROL Register
      40. 7.6.40 TS_LINE_HI Register
      41. 7.6.41 TS_LINE_LO Register
      42. 7.6.42 TS_STATUS Register
      43. 7.6.43 TIMESTAMP_P0_HI Register
      44. 7.6.44 TIMESTAMP_P0_LO Register
      45. 7.6.45 TIMESTAMP_P1_HI Register
      46. 7.6.46 TIMESTAMP_P1_LO Register
      47. 7.6.47 RESERVED Register
      48. 7.6.48 CSI_CTL Register
      49. 7.6.49 CSI_CTL2 Register
      50. 7.6.50 CSI_STS Register
      51. 7.6.51 CSI_TX_ICR Register
      52. 7.6.52 CSI_TX_ISR Register
      53. 7.6.53 CSI_TEST_CTL Register
      54. 7.6.54 CSI_TEST_PATT_HI Register
      55. 7.6.55 CSI_TEST_PATT_LO Register
      56. 7.6.56 RESERVED Register
      57. 7.6.57 RESERVED Register
      58. 7.6.58 RESERVED Register
      59. 7.6.59 RESERVED Register
      60. 7.6.60 RESERVED Register
      61. 7.6.61 RESERVED Register
      62. 7.6.62 RESERVED Register
      63. 7.6.63 AEQ_CTL1 Register
      64. 7.6.64 AEQ_ERR_THOLD Register
      65. 7.6.65 RESERVED Register
      66. 7.6.66 FPD3_CAP Register
      67. 7.6.67 RAW_EMBED_DTYPE Register
      68. 7.6.68 FPD3_PORT_SEL Register
      69. 7.6.69 RX_PORT_STS1 Register
      70. 7.6.70 RX_PORT_STS2 Register
      71. 7.6.71 RX_FREQ_HIGH Register
      72. 7.6.72 RX_FREQ_LOW Register
      73. 7.6.73 SENSOR_STS_0 Register
      74. 7.6.74 SENSOR_STS_1 Register
      75. 7.6.75 SENSOR_STS_2 Register
      76. 7.6.76 SENSOR_STS_3 Register
      77. 7.6.77 RX_PAR_ERR_HI Register
      78. 7.6.78 RX_PAR_ERR_LO Register
      79. 7.6.79 BIST_ERR_COUNT Register
      80. 7.6.80 BCC_CONFIG Register
      81. 7.6.81 DATAPATH_CTL1 Register
      82. 7.6.82 DATAPATH_CTL2 Register
      83. 7.6.83 SER_ID Register
      84. 7.6.84 SER_ALIAS_ID Register
      85. 7.6.85 SlaveID[0] Register
      86. 7.6.86 SlaveID[1] Register
      87. 7.6.87 SlaveID[2] Register
      88. 7.6.88 SlaveID[3] Register
      89. 7.6.89 SlaveID[4] Register
      90. 7.6.90 SlaveID[5] Register
      91. 7.6.91 SlaveID[6] Register
      92. 7.6.92 SlaveID[7] Register
      93. 7.6.93 SlaveAlias[0] Register
      94. 7.6.94 SlaveAlias[1] Register
      95. 7.6.95 SlaveAlias[2] Register
      96. 7.6.96 SlaveAlias[3] Register
      97. 7.6.97 SlaveAlias[4] Register
      98. 7.6.98 SlaveAlias[5] Register
      99. 7.6.99 SlaveAlias[6] Register
      100. 7.6.100SlaveAlias[7] Register
      101. 7.6.101PORT_CONFIG Register
      102. 7.6.102BC_GPIO_CTL0 Register
      103. 7.6.103BC_GPIO_CTL1 Register
      104. 7.6.104RAW10_ID Register
      105. 7.6.105RAW12_ID Register
      106. 7.6.106CSI_VC_MAP Register
      107. 7.6.107LINE_COUNT_HI Register
      108. 7.6.108LINE_COUNT_LO Register
      109. 7.6.109LINE_LEN_1 Register
      110. 7.6.110LINE_LEN_0 Register
      111. 7.6.111FREQ_DET_CTL Register
      112. 7.6.112MAILBOX_1 Register
      113. 7.6.113MAILBOX_2 Register
      114. 7.6.114CSI_RX_STS Register
      115. 7.6.115CSI_ERR_COUNTER Register
      116. 7.6.116PORT_CONFIG2 Register
      117. 7.6.117PORT_PASS_CTL Register
      118. 7.6.118SEN_INT_RISE_CTL Register
      119. 7.6.119SEN_INT_FALL_CTL Register
      120. 7.6.120RESERVED Register
      121. 7.6.121REFCLK_FREQ Register
      122. 7.6.122RESERVED Register
      123. 7.6.123IND_ACC_CTL Register
      124. 7.6.124IND_ACC_ADDR Register
      125. 7.6.125IND_ACC_DATA Register
      126. 7.6.126BIST Control Register
      127. 7.6.127RESERVED Register
      128. 7.6.128RESERVED Register
      129. 7.6.129RESERVED Register
      130. 7.6.130RESERVED Register
      131. 7.6.131MODE_IDX_STS Register
      132. 7.6.132LINK_ERROR_COUNT Register
      133. 7.6.133FPD3_ENC_CTL Register
      134. 7.6.134RESERVED Register
      135. 7.6.135FV_MIN_TIME Register
      136. 7.6.136RESERVED Register
      137. 7.6.137GPIO_PD_CTL Register
      138. 7.6.138RESERVED Register
      139. 7.6.139PORT_DEBUG Register
      140. 7.6.140AEQ_CTL2 Register
      141. 7.6.141AEQ_STATUS Register
      142. 7.6.142ADAPTIVE EQ BYPASS Register
      143. 7.6.143AEQ_MIN_MAX Register
      144. 7.6.144RESERVED Register
      145. 7.6.145RESERVED Register
      146. 7.6.146PORT_ICR_HI Register
      147. 7.6.147PORT_ICR_LO Register
      148. 7.6.148PORT_ISR_HI Register
      149. 7.6.149PORT_ISR_LO Register
      150. 7.6.150FC_GPIO_STS Register
      151. 7.6.151FC_GPIO_ICR Register
      152. 7.6.152SEN_INT_RISE_STS Register
      153. 7.6.153SEN_INT_FALL_STS Register
      154. 7.6.154FPD3_RX_ID0 Register
      155. 7.6.155FPD3_RX_ID1 Register
      156. 7.6.156FPD3_RX_ID2 Register
      157. 7.6.157FPD3_RX_ID3 Register
      158. 7.6.158FPD3_RX_ID4 Register
      159. 7.6.159FPD3_RX_ID5 Register
      160. 7.6.160I2C_RX0_ID Register
      161. 7.6.161I2C_RX1_ID Register
      162. 7.6.162RESERVED Register
      163. 7.6.163RESERVED Register
      164. 7.6.164Indirect Access Registers
      165. 7.6.165Reserved Register
      166. 7.6.166PGEN_CTL Register
      167. 7.6.167PGEN_CFG Register
      168. 7.6.168PGEN_CSI_DI Register
      169. 7.6.169PGEN_LINE_SIZE1 Register
      170. 7.6.170PGEN_LINE_SIZE0 Register
      171. 7.6.171PGEN_BAR_SIZE1 Register
      172. 7.6.172PGEN_BAR_SIZE0 Register
      173. 7.6.173PGEN_ACT_LPF1 Register
      174. 7.6.174PGEN_ACT_LPF0 Register
      175. 7.6.175PGEN_TOT_LPF1 Register
      176. 7.6.176PGEN_TOT_LPF0 Register
      177. 7.6.177PGEN_LINE_PD1 Register
      178. 7.6.178PGEN_LINE_PD0 Register
      179. 7.6.179PGEN_VBP Register
      180. 7.6.180PGEN_VFP Register
      181. 7.6.181PGEN_COLOR0 Register
      182. 7.6.182PGEN_COLOR1 Register
      183. 7.6.183PGEN_COLOR2 Register
      184. 7.6.184PGEN_COLOR3 Register
      185. 7.6.185PGEN_COLOR4 Register
      186. 7.6.186PGEN_COLOR5 Register
      187. 7.6.187PGEN_COLOR6 Register
      188. 7.6.188PGEN_COLOR7 Register
      189. 7.6.189PGEN_COLOR8 Register
      190. 7.6.190PGEN_COLOR9 Register
      191. 7.6.191PGEN_COLOR10 Register
      192. 7.6.192PGEN_COLOR11 Register
      193. 7.6.193PGEN_COLOR12 Register
      194. 7.6.194PGEN_COLOR13 Register
      195. 7.6.195PGEN_COLOR14 Register
      196. 7.6.196RESERVED Register
      197. 7.6.197CSI0_TCK_PREP Register
      198. 7.6.198CSI0_TCK_ZERO Register
      199. 7.6.199CSI0_TCK_TRAIL Register
      200. 7.6.200CSI0_TCK_POST Register
      201. 7.6.201CSI0_THS_PREP Register
      202. 7.6.202CSI0_THS_ZERO Register
      203. 7.6.203CSI0_THS_TRAIL Register
      204. 7.6.204CSI0_THS_EXIT Register
      205. 7.6.205CSI0_TPLX Register
  8. Application and Implementation
    1. 8.1Application Information
      1. 8.1.1System
      2. 8.1.2Power Over Coax
    2. 8.2Typical Application
      1. 8.2.1Design Requirements
      2. 8.2.2Detailed Design Procedure
      3. 8.2.3Application Curves
    3. 8.3System Examples
  9. Power Supply Recommendations
    1. 9.1VDD and VDDIO Power Supply
    2. 9.2Power-Up Sequencing
      1. 9.2.1PDB Pin
      2. 9.2.2System Initialization
  10. 10PCB Layout
    1. 10.1PCB Layout Guidelines
      1. 10.1.1Ground
      2. 10.1.2Routing FPD-Link III Signal Traces and PoC Filter
      3. 10.1.3Routing CSI-2 Signal Traces
    2. 10.2Layout Examples
  11. 11Device and Documentation Support
    1. 11.1Device Support
      1. 11.1.1Development Support
    2. 11.2Documentation Support
      1. 11.2.1Related Documentation
    3. 11.3Receiving Notification of Documentation Updates
    4. 11.4Community Resources
    5. 11.5Trademarks
    6. 11.6Electrostatic Discharge Caution
    7. 11.7Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Features

  • AEC-Q100 Qualified for Automotive Applications:
    • Device Temperature Grade 2: –40℃ to +105℃ Ambient Operating Temperature Range
    • Device HBM ESD Classification Level ±4 kV
    • Device CDM ESD Classification Level C5
  • Dual Deserializer Hub Aggregates One or Two Active Sensors Over FPD-Link III Interface
  • Power-over-Coax (PoC) compatible Transceiver
  • MIPI DPHY Version 1.2 / CSI-2 Version 1.3 Compliant
    • CSI-2 Output Ports
    • Supports 1, 2, 3, 4 Data Lanes
    • CSI-2 Data Rate Scalable for 400 Mbps / 800 Mbps / 1.5 Gbps / 1.6 Gbps each Data Lane
    • Programmable Data Types
    • Four Virtual Channels
    • ECC and CRC Generation
  • Ultra-low Data and Control Path Latency
  • Supports Single-Ended Coaxial or Shielded Twisted-Pair (STP) Cable
  • Adaptive Receive Equalization
  • I2C With Fast-Mode Plus up to 1 Mbps
  • Flexible GPIOs for Camera Synchronization and Diagnostics
  • Compatible with DS90UB953-Q1, DS90UB933-Q1 and DS90UB913A-Q1 Serializers
  • Line Fault Detection and Advanced Diagnostics
  • ISO 10605 and IEC 61000-4-2 ESD Compliant

Applications

  • Automotive ADAS
    • Rear View Cameras (RVC)
    • Surround View Systems (SVS)
    • Camera Monitor Systems (CMS)
    • Forward Vision Cameras (FC)
    • Driver Monitoring Systems (DMS)
    • Satellite RADAR, Time of Flight (ToF) and LIDAR Sensor Modules
  • Security and Surveillance

Description

The DS90UB954-Q1 is a versatile dual deserializer hub capable of receiving serialized sensor data from one or two independent sources through an FPD-Link III interface. When paired with a DS90UB953-Q1 serializer, the DS90UB954-Q1 receives data from imagers, supporting 2MP/60fps and 4MP/30fps cameras as well as satellite RADAR and other sensors such as ToF and LIDAR. Data is received and aggregated into a MIPI CSI-2 compliant output for interconnect to a downstream processor. For sensors with DS90UB933-Q1 and DS90UB913A-Q1 serializers, the DS90UB954-Q1 receives and aggregates data from one or two sensors including Full HD 1080p 2MP 60/fps imager sensors. When configuring the CSI-2 interface for 2-lane operation a duplicate MIPI CSI-2 clock lane is available to provide a replicated output. Replication mode creates two copies of the aggregated video stream for data logging and parallel processing.

The DS90UB954-Q1 and partner DS90UB953-Q1 chipset is AEC-Q100 qualified and designed to receive data across either 50-Ω single-ended coaxial or 100-Ω differential STP cables. The deserializer hub is ideal for Power-over-Coax applications and the receive equalizer automatically adapts to compensate for cable loss characteristics with no additional programming required, including degradation over time.

Each FPD-Link III interface includes a separate low latency bidirectional control channel (BCC) that continuously conveys I2C, GPIO, and other control information. GPIO signals purposed for sensor synchronization and diagnostic features also make use of the BCC.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
DS90UB954-Q1VQFN (48)7.00 mm × 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Schematic

DS90UB954-Q1 954_block_diagram_v2.gif

Revision History

DATEREVISIONNOTES
August 2017*Initial release