DS90LV804
- 800 Mbps Data Rate per Channel
- Low Output Skew and Jitter
- LVDS/CML/LVPECL Compatible Input, LVDS Output
- On-Chip 100Ω Input and Output Termination
- 12 kV ESD Protection on LVDS Outputs
- Single 3.3V Supply
- Very Low Power Consumption
- Industrial -40 to +85°C Temperature Range
- Small WQFN Package Footprint
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The DS90LV804 is a four channel 800 Mbps LVDS buffer/repeater. In many large systems, signals are distributed across cables and signal integrity is highly dependent on the data rate, cable type, length, and the termination scheme.
In order to maximize signal integrity, the DS90LV804 features both an internal input and output (source) termination to eliminate these extra components from the board, and to also place the terminations as close as possible to receiver inputs and driver output. This is especially significant when driving longer cables.
The DS90LV804, available in the WQFN (Leadless Leadframe Package) package, minimizes the footprint, and improves system performance.
An output enable pin is provided, which allows the user to place the LVDS outputs and internal biasing generators in a TRI-STATE, low power mode.
The differential inputs interface to LVDS, and Bus LVDS signals such as those on TI's 10-, 16-, and 18- bit Bus LVDS SerDes, as well as CML and LVPECL. The differential inputs are internally terminated with a 100Ω resistor to improve performance and minimize board space. This function is especially useful for boosting signals over lossy cables or point-to-point backplane configurations.
技术文档
类型 | 标题 | 下载最新的英语版本 | 日期 | |||
---|---|---|---|---|---|---|
* | 数据表 | DS90LV804 4-Channel 800 Mbps LVDS Buffer/Repeater 数据表 (Rev. L) | 2013年 5月 16日 | |||
应用手册 | Signaling Rate vs. Distance for Differential Buffers | 2010年 1月 26日 | ||||
白皮书 | Making the Most of Your LVDS - 5 Tips for Buffering Signal Integrity Headaches | 2001年 8月 1日 | ||||
应用手册 | An Overview of LVDS Technology | 1998年 10月 5日 |
设计和开发
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封装 | 引脚 | 下载 |
---|---|---|
WQFN (RTV) | 32 | 查看选项 |
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