DS90CR285

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+3.3V 上升沿数据选通 LVDS 28 位 频道链接变送器 - 66MHz

产品详情

Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DGG) 56 113.4 mm² 14 x 8.1
  • Single +3.3V Supply
  • Chipset (Tx + Rx) Power Consumption <250 mW (typ)
  • Power-Down Mode (<0.5 mW total)
  • Up to 231 Megabytes/sec Bandwidth
  • Up to 1.848 Gbps Data Throughput
  • Narrow Bus Reduces Cable Size
  • 290 mV Swing LVDS Devices for Low EMI
  • +1V Common Mode Range (Around +1.2V)
  • PLL Requires no External Components
  • Both Devices are Offered in a Low Profile 56-Lead TSSOP Package
  • Rising Edge Data Strobe
  • Compatible with TIA/EIA-644 LVDS Standard
  • ESD Rating > 7 kV
  • Operating Temperature: −40°C to +85°C

All trademarks are the property of their respective owners.

  • Single +3.3V Supply
  • Chipset (Tx + Rx) Power Consumption <250 mW (typ)
  • Power-Down Mode (<0.5 mW total)
  • Up to 231 Megabytes/sec Bandwidth
  • Up to 1.848 Gbps Data Throughput
  • Narrow Bus Reduces Cable Size
  • 290 mV Swing LVDS Devices for Low EMI
  • +1V Common Mode Range (Around +1.2V)
  • PLL Requires no External Components
  • Both Devices are Offered in a Low Profile 56-Lead TSSOP Package
  • Rising Edge Data Strobe
  • Compatible with TIA/EIA-644 LVDS Standard
  • ESD Rating > 7 kV
  • Operating Temperature: −40°C to +85°C

All trademarks are the property of their respective owners.

The DS90CR285 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CR286 receiver converts the LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 66 MHz, 28 bits of TTL data are transmitted at a rate of 462 Mbps per LVDS data channel. Using a 66 MHz clock, the data throughput is 1.848 Gbit/s (231 Mbytes/s).

The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 28-bit wide data and one clock, up to 58 conductors are required. With the Channel Link chipset as few as 11 conductors (4 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor.

The 28 LVCMOS/LVTTL inputs can support a variety of signal combinations. For example, seven 4-bit nibbles or three 9-bit (byte + parity) and 1 control.

The DS90CR285 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CR286 receiver converts the LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 66 MHz, 28 bits of TTL data are transmitted at a rate of 462 Mbps per LVDS data channel. Using a 66 MHz clock, the data throughput is 1.848 Gbit/s (231 Mbytes/s).

The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 28-bit wide data and one clock, up to 58 conductors are required. With the Channel Link chipset as few as 11 conductors (4 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor.

The 28 LVCMOS/LVTTL inputs can support a variety of signal combinations. For example, seven 4-bit nibbles or three 9-bit (byte + parity) and 1 control.

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类型 标题 下载最新的英语版本 日期
* 数据表 DS90CR285/DS90CR286 3.3V Rising Edge Data Strobe LVDS 28Bit Channel Link- 66MHz 数据表 (Rev. C) 2013年 3月 5日
应用手册 High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 2018年 11月 9日
应用手册 AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (Rev. A) 2018年 8月 3日
EVM 用户指南 DS90CR285-86ATQEVM User's Guide 2016年 8月 22日
应用手册 Receiver Skew Margin for Channel Link I and FPD Link I Devices 2016年 1月 13日
应用手册 Improving the Robustness of Channel Link Designs with Channel Link II Ser/Des (Rev. A) 2013年 4月 26日
设计指南 Channel Link I Design Guide 2007年 3月 29日
应用手册 Multi-Drop Channel-Link Operation 2004年 10月 4日
应用手册 CHANNEL LINK Moving and Shaping Information In Point-To-Point Applications 1998年 10月 5日

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评估板

DS90CR285-86ATQEVM — DS90CR285 和 DS90CR286AT-Q1 通道链路 I 串行器/解串器评估模块

DS90CR285-86ATQEVM 包含发送器 (Tx) 板、接收器 (Rx) 板和连接电缆。此套件使用户可以通过低电压差动信号 (LVDS) 从测试设备或图形控制器连接到接收器板。DS90CR285-86ATQEVM 可用于多显示应用的性能评估和初始系统原型设计。
用户指南: PDF
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评估板

FLINK3V8BT-85 — 用于 FPD 链接系列串行器和解串器 LVDS 器件的评估套件

FPD-Link evaluation kit contains a Transmitter (Tx) board, a Receiver (Rx) board along with interfacing cables. This kit will demonstrate the chipsets interfacing from test equipment or a graphics controller using Low Voltage Differential Signaling (LVDS) to a receiver board.

The Transmitter board (...)

用户指南: PDF
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仿真模型

DS90CR285 IBIS Model

SNLM037.ZIP (4 KB) - IBIS Model
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英语版 (Rev.A): PDF
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