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DS90C387A

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双像素 LVDS 显示接口 / FPD 链接变送器

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DS90C387A

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产品详情

Function Serializer Color depth (bps) 24 Input compatibility LVCMOS Output compatibility FPD-Link LVDS Features Low-EMI Point-to-Point Communication Applications In-vehicle Infotainment (IVI) EMI reduction LVDS Rating Catalog Operating temperature range (°C) -10 to 70
Function Serializer Color depth (bps) 24 Input compatibility LVCMOS Output compatibility FPD-Link LVDS Features Low-EMI Point-to-Point Communication Applications In-vehicle Infotainment (IVI) EMI reduction LVDS Rating Catalog Operating temperature range (°C) -10 to 70
QFP (NEZ) 100 256 mm² 16 x 16
  • Supports SVGA through QXGA panel resolutions
  • 32.5 to 112/170MHz clock support
  • Drives long, low cost cables
  • Up to 5.7 Gbps bandwidth
  • Pre-emphasis reduces cable loading effects
  • Dual pixel architecture supports interface to GUI and timing controller; optional single pixel transmitter inputs support single pixel GUI interface
  • Transmitter rejects cycle-to-cycle jitter
  • 5V tolerant on data and control input pins
  • Programmable transmitter data and control strobe select (rising or falling edge strobe)
  • Backward compatible with FPD-Link
  • Compatible with ANSI/TIA/EIA-644-1995 LVDS Standard

TRI-STATE® is a registered trademark of National Semiconductor Corporation.
  • Supports SVGA through QXGA panel resolutions
  • 32.5 to 112/170MHz clock support
  • Drives long, low cost cables
  • Up to 5.7 Gbps bandwidth
  • Pre-emphasis reduces cable loading effects
  • Dual pixel architecture supports interface to GUI and timing controller; optional single pixel transmitter inputs support single pixel GUI interface
  • Transmitter rejects cycle-to-cycle jitter
  • 5V tolerant on data and control input pins
  • Programmable transmitter data and control strobe select (rising or falling edge strobe)
  • Backward compatible with FPD-Link
  • Compatible with ANSI/TIA/EIA-644-1995 LVDS Standard

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

The DS90C387A/DS90CF388A transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL data and 3 control bits into 8 LVDS (Low Voltage Differential Signalling) data streams. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 784Mbps, providing a total throughput of 5.7Gbps (714 Megabytes per second).

The LDI chipset is improved over prior generations of FPD-Link devices and offers higher bandwidth support and longer cable drive. To increase bandwidth, the maximum pixel clock rate is increased to 112 MHz and 8 serialized LVDS outputs are provided. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects.

The DS90C387A transmitter provides a second LVDS output clock. Both LVDS clocks are identical. This feature supports backward compatibility with the previous generation of FPD-Link Receivers - the second clock allows the transmitter to interface to panels using a 'dual pixel' configuration of two 24-bit or 18-bit FPD-Link receivers.

This chipset is an ideal means to solve EMI and cable size problems for high-resolution flat panel applications. It provides a reliable interface based on LVDS technology that delivers the bandwidth needed for high-resolution panels while maximizing bit times, and keeping clock rates low to reduce EMI and shielding requirements. For more details, please refer to the "Applications Information" section of this datasheet.

The DS90C387A/DS90CF388A transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL data and 3 control bits into 8 LVDS (Low Voltage Differential Signalling) data streams. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 784Mbps, providing a total throughput of 5.7Gbps (714 Megabytes per second).

The LDI chipset is improved over prior generations of FPD-Link devices and offers higher bandwidth support and longer cable drive. To increase bandwidth, the maximum pixel clock rate is increased to 112 MHz and 8 serialized LVDS outputs are provided. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects.

The DS90C387A transmitter provides a second LVDS output clock. Both LVDS clocks are identical. This feature supports backward compatibility with the previous generation of FPD-Link Receivers - the second clock allows the transmitter to interface to panels using a 'dual pixel' configuration of two 24-bit or 18-bit FPD-Link receivers.

This chipset is an ideal means to solve EMI and cable size problems for high-resolution flat panel applications. It provides a reliable interface based on LVDS technology that delivers the bandwidth needed for high-resolution panels while maximizing bit times, and keeping clock rates low to reduce EMI and shielding requirements. For more details, please refer to the "Applications Information" section of this datasheet.
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类型 标题 下载最新的英语版本 日期
* 数据表 DS90C387A/DS90CF388A Dual Pixel LVDS Display Interface / FPD-Link 数据表 (Rev. D) 2006年 2月 3日
应用手册 High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 2018年 11月 9日
应用手册 How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) 2018年 6月 29日
应用手册 AN-1032 An Introduction to FPD-Link (Rev. C) 2017年 8月 8日
应用手册 TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map 2004年 5月 15日
应用手册 AN-1056 STN Application Using FPD-Link 2004年 5月 14日
应用手册 AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines 2004年 5月 14日
应用手册 LVDS goes the distance! 2003年 2月 17日

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