DS90C387A 双像素 LVDS 显示接口 / FPD 链接发送器 | 德州仪器 TI.com.cn

DS90C387A (正在供货) 双像素 LVDS 显示接口 / FPD 链接发送器

双像素 LVDS 显示接口 / FPD 链接发送器 - DS90C387A


The DS90C387A/DS90CF388A transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL data and 3 control bits into 8 LVDS (Low Voltage Differential Signalling) data streams. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 784Mbps, providing a total throughput of 5.7Gbps (714 Megabytes per second).

The LDI chipset is improved over prior generations of FPD-Link devices and offers higher bandwidth support and longer cable drive. To increase bandwidth, the maximum pixel clock rate is increased to 112 MHz and 8 serialized LVDS outputs are provided. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects.

The DS90C387A transmitter provides a second LVDS output clock. Both LVDS clocks are identical. This feature supports backward compatibility with the previous generation of FPD-Link Receivers - the second clock allows the transmitter to interface to panels using a 'dual pixel' configuration of two 24-bit or 18-bit FPD-Link receivers.

This chipset is an ideal means to solve EMI and cable size problems for high-resolution flat panel applications. It provides a reliable interface based on LVDS technology that delivers the bandwidth needed for high-resolution panels while maximizing bit times, and keeping clock rates low to reduce EMI and shielding requirements. For more details, please refer to the "Applications Information" section of this datasheet.


  • Supports SVGA through QXGA panel resolutions
  • 32.5 to 112/170MHz clock support
  • Drives long, low cost cables
  • Up to 5.7 Gbps bandwidth
  • Pre-emphasis reduces cable loading effects
  • Dual pixel architecture supports interface to GUI and timing controller; optional single pixel transmitter inputs support single pixel GUI interface
  • Transmitter rejects cycle-to-cycle jitter
  • 5V tolerant on data and control input pins
  • Programmable transmitter data and control strobe select (rising or falling edge strobe)
  • Backward compatible with FPD-Link
  • Compatible with ANSI/TIA/EIA-644-1995 LVDS Standard

TRI-STATE® is a registered trademark of National Semiconductor Corporation.


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Part number 立即下单 Function Color depth (bpp) Pixel clock min (MHz) Pixel clock (Max) (MHz) Input compatibility Output compatibility Features Signal conditioning EMI reduction Diagnostics Total throughput (Mbps) Rating Operating temperature range (C) Package Group Package size: mm2:W x L (PKG)
DS90C387A 立即下单 Transmitter     24     32.5     170     CMOS
FPD-Link LVDS     Supports SVGA through QXGA Panel Resolutions
Dual Pixel Architecture Supports Interface to GUI and Timing Controller    
Cable Deskew Function    
LVDS         5700     Catalog     -10 to 70     TQFP | 100     100TQFP: 256 mm2: 16 x 16 (TQFP | 100)