LVDS Quad CMOS Differential Line Receiver - DS90C032QML-SP

DS90C032QML-SP (正在供货)

LVDS Quad CMOS Differential Line Receiver

 

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描述

The DS90C032 is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates.

The DS90C032 accepts low voltage differential input signals and translates them to CMOS (TTL compatible) output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports OPEN Failsafe and terminated (100Ω) input Failsafe with the addition of external failsafe biasing. Receiver output will be HIGH for both Failsafe conditions.

The DS90C032 provides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present.

The DS90C032 and companion line driver (DS90C031) provide a new alternative to high power pseudo-ECL devices for high speed point-to-point interface applications.

特性

  • Single Event Latchup (SEL) Immune 120 MeV-cm2/mg
  • High Impedance LVDS Inputs with Power-Off.
  • Accepts Small Swing (330 mV) Differential Signal Levels
  • Low Power Dissipation
  • Low Differential Skew
  • Low Chip to Chip Skew
  • Pin Compatible with DS26C32A
  • Compatible with IEEE 1596.3 SCI LVDS Standard

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参数 与其它产品相比 LVDS/M-LVDS/ECL/CML 产品

 
No. of Tx
No. of Rx
Input Signal
Output Signal
ESD HBM (kV)
ICC (Max) (mA)
Function
Rating
Operating Temperature Range (C)
Package Group
Package Size: mm2:W x L (PKG)
DS90C032QML-SP DS90LV032AQML-SP
4    4   
4    4   
LVDS    LVDS   
TTL    LVTTL   
2    4.5   
11    15   
Receiver    Receiver   
Space    Space   
-55 to 125    -55 to 85   
CFP    CFP   
See datasheet (CFP)    See datasheet (CFP)   

其它合格版本 DS90C032QML-SP

版本 器件型号 定义
军事应用 DS90C032QML 获 QML 认证,用于军事与国防应用