DS25BR110
- DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation
- Four Levels of Receive Equalization Reduce ISI Jitter
- On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space
- 7 kV ESD on LVDS I/O Pins Protects Adjoining Components
- Small 3 mm x 3 mm 8-WSON Space Saving Package
All trademarks are the property of their respective owners.
The DS25BR110 is a single channel 3.125 Gbps LVDS buffer optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced metallic cables. A fully differential signal path ensures exceptional signal integrity and noise immunity.
The DS25BR110 features four levels of receive equalization (EQ), making it ideal for use as a receiver device. Other LVDS devices with similar IO characteristics include the following products. The DS25BR120 features four levels of pre-emphasis for use as an optimized driver device, while the DS25BR100 features both pre-emphasis and equalization for use as an optimized repeater device. The DS25BR150 is a buffer/repeater with the lowest power consumption and does not feature transmit pre-emphasis nor receive equalization.
Wide input common mode range allows the receiver to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires minimal space on the board while the flow-through pinout allows easy board layout. The differential inputs and outputs are internally terminated with a 100Ω resistor to lower device input and output return losses, reduce component count, and further minimize board space.
技术文档
| 类型 | 标题 | 下载最新的英语版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 数据表 | DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization 数据表 (Rev. E) | 2013年 4月 14日 | |||
| 应用手册 | 低压差分信号 (LVDS) 在 LED 灯墙中的应用 | 英语版 | 2022年 5月 19日 | |||
| 应用手册 | Applications of Low-Voltage Differential Signaling (LVDS) in Ultrasound Scanners | 2019年 6月 29日 | ||||
| 应用手册 | LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A) | 2013年 4月 29日 | ||||
| 应用手册 | AN-1957 LVDS Signal Conditioners Reduce Data-Dependent Jitter (Rev. A) | 2013年 4月 26日 | ||||
| 用户指南 | 3.125 Gbps LVDS Buffers with Pre-emphasis and Equalization User Guide | 2012年 1月 25日 | ||||
| 应用手册 | LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (cn) | 最新英语版本 (Rev.A) | 2008年 9月 4日 | |||
| 应用手册 | Extending the Signal Path Over Data Trans Lines Using LVDS Signal Conditioning | 2007年 8月 2日 |
设计和开发
如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。
DS25BR100EVK — 具有发送预强调和接收均衡功能的 3.125 Gbps LVDS 单通道缓冲器系列
The DS25BR100EVK is an evaluation kit designed for demonstrating performance of the 3.125 Gbps LVDS Single Channel Buffers with Transmit Pre-Emphasis (PE) and Receive Equalization (EQ) family (DS25BR100, DS25BR110 and DS25BR120). The evaluation kit provides all three devices on a single board and (...)
PSPICE-FOR-TI — 适用于 TI 设计和模拟工具的 PSpice®
借助 PSpice for TI 的设计和仿真环境及其内置的模型库，您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案，然后再进行布局和制造，可缩短产品上市时间并降低开发成本。
在 PSpice for TI 设计和仿真工具中，您可以搜索 TI (...)
TINA-TI — 基于 SPICE 的模拟仿真程序
TINA-TI 安装需要大约 500MB。直接安装，如果想卸载也很容易。我们相信您肯定会爱不释手。
TINA 是德州仪器 (TI) 专有的 DesignSoft 产品。该免费版本具有完整的功能，但不支持完整版 TINA 所提供的某些其他功能。
如需获取可用 TINA-TI 模型的完整列表，请参阅：SpiceRack - 完整列表
需要 HSpice (...)
| 封装 | 引脚 | 下载 |
|---|---|---|
| WSON (NGQ) | 8 | 查看选项 |
订购和质量
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/时基故障估算
- 材料成分
- 鉴定摘要
- 持续可靠性监测
- 制造厂地点
- 封装厂地点
推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。