ZHCSB92G June   2013  – May 2017 DRV8711

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Indexer Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PWM Motor Drivers
      2. 7.3.2  Direct PWM Input Mode
      3. 7.3.3  Microstepping Indexer
      4. 7.3.4  Current Regulation
      5. 7.3.5  Decay Modes
      6. 7.3.6  Blanking Time
      7. 7.3.7  Predrivers
      8. 7.3.8  Configuring Predrivers
      9. 7.3.9  External FET Selection
      10. 7.3.10 Stall Detection
        1. 7.3.10.1 Internal Stall Detection
        2. 7.3.10.2 External Stall Detection
      11. 7.3.11 Protection Circuits
        1. 7.3.11.1 Overcurrent Protection (OCP)
        2. 7.3.11.2 Predriver Fault
        3. 7.3.11.3 Thermal Shutdown (TSD)
        4. 7.3.11.4 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 RESET and SLEEPn Operation
      2. 7.4.2 Microstepping Drive Current
    5. 7.5 Programming
      1. 7.5.1 Serial Data Format
    6. 7.6 Register Maps
      1. 7.6.1 Control Registers
      2. 7.6.2 CTRL Register (Address = 0x00)
      3. 7.6.3 TORQUE Register (Address = 0x01)
      4. 7.6.4 OFF Register (Address = 0x02)
      5. 7.6.5 BLANK Register (Address = 0x03)
      6. 7.6.6 DECAY Register (Address = 0x04)
      7. 7.6.7 STALL Register (Address = 0x05)
      8. 7.6.8 DRIVE Register (Address = 0x06)
      9. 7.6.9 STATUS Register (Address = 0x07)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Sense Resistor
      2. 8.1.2 Optional Series Gate Resistor
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stepper Motor Speed
        2. 8.2.2.2 Current Regulation
        3. 8.2.2.3 Decay Modes
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)(3)
MIN MAX UNIT
Power supply voltage –0.6 60 V
Charge pump voltage (CP2, VCP) –0.6 VM + 12 V
Charge pump voltage (CP1) –0.6 VM + 0.6 V
5-V regulator voltage (V5) –0.6 5.5 V
Internal regulator voltage (VINT) –0.6 2 V
Digital pin voltage (SLEEPn, RESET, STEP/AIN1, DIR/AIN2, BIN1, BIN2, SCS, SCLK, SDATI, SDATO, FAULTn, STALLn/BEMFVn) –0.6 5.5 V
High-side gate drive pin voltage (A1HS, A2HS, B1HS, B2HS) –0.6 VM + 12 V
Low-side gate drive pin voltage (A1LS, A2LS, B1LS, B2LS) –0.6 12 V
Phase node pin voltage (AOUT1, AOUT2, BOUT1, BOUT2) –0.6 VM + 0.6 V
ISENSEx pin voltage (AISENP, AISENN, BISENP, BISENN) –0.7 0.7 V
BEMF pin voltage (BEMF) –0.6 5.5 V
Operating virtual junction temperature, TJ –40 150 °C
Storage temperature, Tstg –60 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Power dissipation and thermal limits must be observed.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VM Motor power supply voltage 8 52 V
IVS V5 external load current 0 10 mA
TA Operating ambient temperature -40 85 °C

6.4 Thermal Information

THERMAL METRIC(1) DRV8711 UNIT
DCP (HTSSOP)
38 PINS
RθJA Junction-to-ambient thermal resistance 32.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 17.2 °C/W
RθJB Junction-to-board thermal resistance 14.3 °C/W
ψJT Junction-to-top characterization parameter 0.5 °C/W
ψJB Junction-to-board characterization parameter 14.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES
IVM VM operating supply current VM = 24 V 17 20 mA
IVMQ VM sleep mode supply current VM = 24 V, SLEEPn = 0, TA = 25°C 65 98 μA
VUVLO VM undervoltage lockout voltage VM rising 7.1 8 V
VM falling 6.3
INTERNAL LINEAR REGULATORS
V5 V5 output voltage VM ≥ 12 V, IOUT = 1 mA – 10 mA 4.8 5 5.2 V
VINT VINT voltage No external load – reference only 1.7 1.8 1.9 V
LOGIC-LEVEL INPUTS
VIL Input low voltage 0.8 V
VIH Input high voltage 1.5 V
VHYS Input hysteresis voltage 300 mV
IIL Input low current VIN = 0 V –5 5 μA
IIH Input high current VIN = 5 V 30 50 70 μA
SDATAO, STALLn, FAULTn OUTPUTS (OPEN-DRAIN OUTPUTS)
VOL Output low voltage IO = 5 mA 0.5 V
IOH Output high leakage current VO = 3.3 V 1 µA
MOSFET DRIVERS
VOUTH High-side gate drive output voltage VM = 24 V, IO = 100 μA VM+10 V
VOUTL Low-side gate drive output voltage VM = 24 V, IO = 100 μA 10 V
tDEAD Output dead time digital delay (dead time is enforced in analog circuits) DTIME = 00 400 ns
DTIME = 01 450
DTIME = 10 650
DTIME = 11 850
IOUTH Peak output current gate drive (source) IDRIVEP = 00 50 mA
IDRIVEP = 01 100
IDRIVEP = 10 150
IDRIVEP = 11 200
IOUTl Peak output current gate drive (sink) IDRIVEN = 00 100 mA
IDRIVEN = 01 150
IDRIVEN = 10 200
IDRIVEN = 11 400
tDRIVE Peak current drive time (source) TDRIVEP = 00 250 ns
TDRIVEP = 01 500
TDRIVEP = 10 1000
TDRIVEP = 11 2000
tDRIVE Peak current drive time (sink) TDRIVEN = 00 250 ns
TDRIVEN = 01 500
TDRIVEN = 10 1000
TDRIVEN = 11 2000
MOTOR DRIVER
tOFF PWM off time adjustment range Set by TOFF register 0.5 128 μs
tBLANK Current sense blanking time Set by TBLANK register 0.5 5.12 μs
PROTECTION CIRCUITS
VOCP Overcurrent protection trip level (Voltage drop across external FET) OCPTH = 00 160 250 320 mV
OCPTH = 01 380 500 580
OCPTH = 10 620 750 850
OCPTH = 11 840 1000 1200
tTSD Thermal shutdown temperature(1) Die temperature 150 160 180 °C
tHYS Thermal shutdown hysteresis 20 °C
CURRENT SENSE AMPLIFIERS
AV Gain ISGAIN = 00 5 V/V
ISGAIN = 01 10
ISGAIN = 10 20
ISGAIN = 11 40
tSET Settling time (to ±1%) ISGAIN = 00, ΔVIN = 400 mV 150 ns
ISGAIN = 01, ΔVIN = 200 mV 300
ISGAIN = 10, ΔVIN = 100 mV 600
ISGAIN = 11, ΔVIN = 50 mV 1.2 µs
VOFS Offset voltage ISGAIN = 00, input shorted 4 mV
VIN Input differential voltage range –600 600 mV
CURRENT CONTROL DACs
Resolution 256 steps
Full-scale step response 10% to 90% 5 µs
VREF Full-scale (reference) voltage 2.50 2.75 3 V
(1) Not tested in production; ensured by design.

6.6 SPI Timing Requirements

over operating free-air temperature range (unless otherwise noted) (see Figure 1)
NO. MIN NOM MAX UNIT
1 tCYC Clock cycle time 250 ns
2 tCLKH Clock high time 25 ns
3 tCLKL Clock low time 25 ns
4 tSU(SDATI) Setup time, SDATI to SCLK 5 ns
5 tH(SDATI) Hold time, SDATI to SCLK 1 ns
6 tSU(SCS) Setup time, SCS to SCLK 5 ns
7 tH(SCS) Hold time, SCS to SCLK 1 ns
8 tL(SCS) Inactive time, SCS (between writes and reads) 100 ns
9 tD(SDATO) Delay time, SCLK to SDATO (during read) 10 ns
tSLEEP Wake time (SLEEPn inactive to high-side gate drive enabled) 1 ms
tRESET Delay from power up or RESETn high until serial interface functional 10 μs

6.7 Indexer Timing Requirements

over operating free-air temperature range (unless otherwise noted) (see Figure 2)
NO. MIN NOM MAX UNIT
1 fSTEP Step frequency 250 kHz
2 tWH(STEP) Pulse duration, STEP high 1.9 μs
3 tWL(STEP) Pulse duration, STEP low 1.9 μs
4 tSU(STEP) Setup time, command to STEP rising 200 ns
5 tH(STEP) Hold time, command to STEP rising 200 ns
DRV8711 SPI_int_tim_req_SLVSC40.gif Figure 1. SPI Timing
DRV8711 ind_tim_req_SLVSC40.gif Figure 2. Indexer Timing

6.8 Typical Characteristics

DRV8711 C005_SLVSC40.png
Figure 3. Operating Current
DRV8711 C007_SLVSC40.png
Figure 5. VCP Minus VM
DRV8711 C006_SLVSC40.png
Figure 4. Sleep Current
DRV8711 C008_SLVSC40.png
Figure 6. V5 No Load