ZHCSDO0A March   2015  – May 2015 DRV8701

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Bridge Control
      2. 7.3.2  Half-Bridge Operation
      3. 7.3.3  Current Regulation
      4. 7.3.4  Amplifier Output SO
        1. 7.3.4.1 SNSOUT
      5. 7.3.5  PWM Motor Gate Drivers
      6. 7.3.6  IDRIVE Pin
      7. 7.3.7  Dead Time
      8. 7.3.8  Propagation Delay
      9. 7.3.9  Overcurrent VDS Monitor
      10. 7.3.10 Charge Pump
      11. 7.3.11 LDO Voltage Regulators
      12. 7.3.12 Gate Drive Clamp
      13. 7.3.13 Protection Circuits
        1. 7.3.13.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.13.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.13.3 Overcurrent Protection (OCP)
        4. 7.3.13.4 Pre-Driver Fault (PDF)
        5. 7.3.13.5 Thermal Shutdown (TSD)
      14. 7.3.14 Reverse Supply Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operating DRV8701 and H-Bridge on Separate Supplies
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Brushed-DC Motor Control
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 External FET Selection
          2. 8.2.1.2.2 IDRIVE Configuration
          3. 8.2.1.2.3 Current Chopping Configuration
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Alternate Application
        1. 8.2.2.1 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 IDRIVE Configuration
        2. 8.2.3.2 VM Boost Voltage
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance Sizing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range referenced with respect to GND (unless otherwise noted) (1)
MIN MAX UNIT
Power supply voltage (VM) –0.3 47 V
Power supply voltage ramp rate (VM) 0 2 V/µs
Charge pump voltage (VCP, CPH) –0.3 VM + 12 V
Charge pump negative switching pin (CPL) –0.3 VM V
Internal logic regulator voltage (DVDD) –0.3 3.8 V
Internal analog regulator voltage (AVDD) –0.3 5.75 V
Control pin voltage (PH, EN, IN1, IN2, nSLEEP, nFAULT, VREF, IDRIVE, SNSOUT) –0.3 5.75 V
High-side gate pin voltage (GH1, GH2) –0.3 VM + 12 V
Continuous phase node pin voltage (SH1, SH2) –1.2 VM + 1.2 V
Pulsed 10 µs phase node pin voltage (SH1, SH2) –2.0 VM + 2 V
Low-side gate pin voltage (GL1, GL2) –0.3 12 V
Continuous shunt amplifier input pin voltage (SP, SN) –0.5 1 V
Pulsed 10-µs shunt amplifier input pin voltage (SP, SN) –1 1 V
Shunt amplifier output pin voltage (SO) –0.3 5.75 V
Open-drain output current (nFAULT, SNSOUT) 0 10 mA
Gate pin source current (GH1, GL1, GH2, GL2) 0 250 mA
Gate pin sink current (GH1, GL1, GH2, GL2) 0 500 mA
Shunt amplifier output pin current (SO) 0 5 mA
Operating junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM) ESD stress voltage(1) ±2000 V
Charged device model (CDM) ESD stress voltage(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VM Power supply voltage range 5.9 45 V
VCC Logic level input voltage 0 5.5 V
VREF Reference RMS voltage range (VREF) 0.3(1) AVDD V
ƒPWM Applied PWM signal (PH/EN or IN1/IN2) 100 kHz
IAVDD AVDD external load current 30(2) mA
IDVDD DVDD external load current 30(2) mA
ISO Shunt amplifier output current loading (SO) 5 mA
TA Operating ambient temperature –40 125 °C
(1) Operational at VREF = 0 to 0.3 V, but accuracy is degraded
(2) Power dissipation and thermal limits must be observed

6.4 Thermal Information

THERMAL METRIC(1) DRV8701 UNIT
RGE (VQFN)
24 PINS
RθJA Junction-to-ambient thermal resistance 34.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 37.1 °C/W
RθJB Junction-to-board thermal resistance 12.2 °C/W
ψJT Junction-to-top characterization parameter 0.6 °C/W
ψJB Junction-to-board characterization parameter 12.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VM, AVDD, DVDD)
VM VM operating voltage 5.9 45 V
IVM VM operating supply current VM = 24 V; nSLEEP high 6 9.5 mA
IVMQ VM sleep mode supply current nSLEEP = 0
VM = 24 V		 TA = 25°C 9 15 μA
TA = 125°C(1) 14 25
tSLEEP Sleep time nSLEEP low to sleep mode 100 μs
tWAKE Wake-up time nSLEEP high to output change 1 ms
tON Turn-on time VM > UVLO to output transition 1 ms
DVDD Internal logic regulator voltage External load 0 to 30 mA 3.0 3.3 3.5 V
AVDD Internal logic regulator voltage External load 0 to 30 mA 4.4 4.8 5.2 V
CHARGE PUMP (VCP, CPH, CPL)
VCP VCP operating voltage VM = 12 V; IVCP = 0 to 12 mA 20.5 21.5 22.5 V
VM = 8 V; IVCP = 0 to 10 mA 13.5 14.4 15
VM = 5.9 V; IVCP = 0 to 8 mA 9.4 9.9 10.4
IVCP Charge pump current capacity VM > 12 V 12 mA
8 V < VM < 12 V 10
5.9 V < VM < 8 V 8
fVCP(1) Charge pump switching frequency VM > UVLO 200 400 700 kHz
CONTROL INPUTS (PH, EN, IN1, IN2, nSLEEP)
VIL Input logic low voltage 0.8 V
VIH Input logic high voltage 1.5 V
VHYS Input logic hysteresis 100 mV
IIL Input logic low current VIN = 0 V –5 5 μA
IIH Input logic high current VIN = 5 V 78 μA
RPD Pulldown resistance 64 115 173 kΩ
tPD Propagation delay PH/EN, IN1/IN2 to GHx/GLx 500 ns
CONTROL OUTPUTS (nFAULT, SNSOUT)
VOL Output logic low voltage IO = 2 mA 0.1 V
IOZ Output high impedance leakage VIN = 5 V –2 2 μA
FET GATE DRIVERS (GH1, GH2, SH1, SH2, GL1, GL2)
VGHS High-side VGS gate drive (gate-to-source) VM > 12 V; VGHS with respect to SHx 8.5 9.5 10.5 V
VM = 8 V; VGHS with respect to SHx 5.5 6.4 7
VM = 5.9 V; VGHS with respect to SHx 3.5 4.0 4.5
VGLS Low-side VGS gate drive (gate-to-source) VM > 12 V 8.5 9.3 10.5 V
VM = 5.9 V 3.9 4.3 4.9
tDEAD Output dead time Observed tDEAD depends on IDRIVE setting 380 ns
tDRIVE Gate drive time 2.5 μs
IDRIVE,SRC Peak source current RIDRIVE < 1 kΩ to GND 6 mA
RIDRIVE = 33 kΩ ±5% to GND 12.5
RIDRIVE = 200 kΩ ±5% to GND, or
RIDRIVE < 1 kΩ to AVDD		 25
RIDRIVE > 500 kΩ ±5% to GND 100
RIDRIVE = 68 kΩ ±5% to AVDD 150
IDRIVE,SNK Peak sink current RIDRIVE < 1 kΩ to GND 12.5 mA
RIDRIVE = 33 kΩ ±5% to GND 25
RIDRIVE = 200 kΩ ±5% to GND 50
RIDRIVE < 1 kΩ to AVDD 200
RIDRIVE > 500 ±5% kΩ to GND 300
RIDRIVE = 68 kΩ ±5% to AVDD 50
IHOLD FET holding current Source current after tDRIVE 6 mA
Sink current after tDRIVE 25
ISTRONG FET hold-off strong pulldown GHx 490 mA
GLx 690
ROFF FET gate hold-off resistor Pulldown GHx to SHx 200 kΩ
Pulldown GLx to GND 150
CURRENT SHUNT AMPLIFIER AND PWM CURRENT CONTROL (SP, SN, SO, VREF)
VVREF VREF input voltage For current internal chopping 0.3(3) AVDD V
AV Amplifier gain 50 < VSP < 200 mV; VSN = GND 18 20 22 V/V
10 < VSP < 50 mV; VSN = GND 16 20 24
VOFF SO offset VSP = VSN = GND 50 250 mV
ISP SP input current VSP = 100 mV; VSN = GND -40 μA
tSET(2) Settling time to ±1% VSP = VSN = GND to
VSP = 100 mV, VSN = GND		 1.5 µs
CSO(2) Allowable SO pin capacitance 1 nF
tOFF PWM current regulation off-time 25 µs
tBLANK PWM blanking time 2 µs
PROTECTION CIRCUITS
VUVLO VM undervoltage lockout VM falling; UVLO report 5.4 5.8 V
VM rising; UVLO recovery 5.6 5.9
VUVLO,HYS VM undervoltage hysteresis Rising to falling threshold 100 mV
tUVLO VM UVLO falling deglitch time VM falling; UVLO report 10 μs
VCPUV Charge pump undervoltage CPUV report VM + 2.8 V
VDS OCP Overcurrent protection trip level, VDS of each external FET High-side FETs: VM – SHx
Low-side FETs: SHx – SP		 0.8 1 V
VSP OCP Overcurrent protection trip level, measured by sense amplifier VSP voltage with respect to GND 0.8 1 V
tOCP Overcurrent deglitch time 4.5 µs
tRETRY Overcurrent retry time 3 ms
TTSD(2) Thermal shutdown temperature Die temperature, TJ 150 °C
THYS(2) Thermal shutdown hysteresis Die temperature, TJ 20 °C
VGS CLAMP Gate drive clamping voltage Positive clamping voltage 10.5 13 V
Negative clamping voltage –1 –0.7 –0.5
(1) Specified by design and characterization data
(2) Specified by design and characterization data
(3) Operational at VREF = 0 to 0.3 V, but accuracy is degraded

6.6 Typical Characteristics

DRV8701 D001_SLVSCX5.gif
Figure 1. Supply Current over VM
DRV8701 D003_SLVSCX5.gif
Figure 3. Sleep Current over VM
DRV8701 D005_SLVSCX5.gif
Figure 5. VCP over Load (TA = 25°C)
DRV8701 D007_SLVSCX5.gif
Figure 7. DVDD Regulator over Load (VM = 12 V)
DRV8701 D009_SLVSCX5.gif
Figure 9. SO Offset over Temperature
DRV8701 D011_SLVSCX5.gif
Figure 11. Amplifier Gain over VM (SP = 50 mV)
DRV8701 D013_SLVSCX5.gif
Figure 13. High-Side IDRIVEP over Temperature (VM = 12 V)
DRV8701 D015_SLVSCX5.gif
Figure 15. 12.5-/25-mA High-Side IDRIVEP over VM
DRV8701 D017_SLVSCX5.gif
Figure 17. 100-/200-mA High-Side IDRIVEP over VM
DRV8701 D002_SLVSCX5.gif
Figure 2. Supply Current over Temperature
DRV8701 D004_SLVSCX5.gif
Figure 4. Sleep Current over Temperature
DRV8701 D006_SLVSCX5.gif
Figure 6. VCP over Load (VM = 5.9 V)
DRV8701 D008_SLVSCX5.gif
Figure 8. AVDD Regulator over Load (VM = 12 V)
DRV8701 D010_SLVSCX5.gif
Figure 10. Amplifier Gain over Temperature
DRV8701 D012_SLVSCX5.gif
Figure 12. Amplifier Gain over VM and Temperature Range
DRV8701 D014_SLVSCX5.gif
Figure 14. 6-/12.5-mA High-Side IDRIVEP over VM
DRV8701 D016_SLVSCX5.gif
Figure 16. 25-/50-mA High-Side IDRIVEP over VM
DRV8701 D018_SLVSCX5.gif
Figure 18. 150-/300-mA High-Side IDRIVEP over VM