SLAS748F March 2011  – August 2015

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - DC Specifications
    6. 6.6 Electrical Characteristics - Digital Specifications
    7. 6.7 Electrical Characteristics - AC Specifications
    8. 6.8 Electrical Characteristics - Phase-Locked Loop Specifications
    9. 6.9 Timing Requirements - Digital Specifications
    10. 6.10Switching Characteristics - AC Specifications
    11. 6.11Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1 Serial Interface
      2. 7.3.2 Data Interface
        1. 7.3.2.1Word-Wide Format
        2. 7.3.2.2Byte-Wide Format
      3. 7.3.3 Input FIFO
      4. 7.3.4 FIFO Modes of Operation
        1. 7.3.4.1Dual Sync Source Mode
        2. 7.3.4.2Single Sync Source Mode
        3. 7.3.4.3Bypass Mode
      5. 7.3.5 Clocking Modes
        1. 7.3.5.1PLL Bypass Mode
        2. 7.3.5.2PLL Mode
      6. 7.3.6 FIR Filters
      7. 7.3.7 Complex Signal Mixer
        1. 7.3.7.1Full Complex Mixer
        2. 7.3.7.2Coarse Complex Mixer
        3. 7.3.7.3Mixer Gain
        4. 7.3.7.4Real Channel Upconversion
      8. 7.3.8 Quadrature Modulation Correction (QMC)
        1. 7.3.8.1Gain and Phase Correction
        2. 7.3.8.2Offset Correction
        3. 7.3.8.3Group Delay Correction
      9. 7.3.9 Temperature Sensor
      10. 7.3.10Data Pattern Checker
      11. 7.3.11Parity Check Test
        1. 7.3.11.1Word-by-Word Parity
        2. 7.3.11.2Block Parity
      12. 7.3.12DAC3482 Alarm Monitoring
      13. 7.3.13LVPECL Inputs
      14. 7.3.14LVDS Inputs
      15. 7.3.15Unused LVDS Port Termination
      16. 7.3.16CMOS Digital Inputs
      17. 7.3.17Reference Operation
      18. 7.3.18DAC Transfer Function
      19. 7.3.19Analog Current Outputs
    4. 7.4Device Functional Modes
      1. 7.4.1Multi-Device Synchronization
        1. 7.4.1.1Multi-Device Synchronization: PLL Bypassed with Dual Sync Sources Mode
        2. 7.4.1.2Multi-Device Synchronization: PLL Enabled with Dual Sync Sources Mode
        3. 7.4.1.3Multi-Device Operation: Single Sync Source Mode
    5. 7.5Programming
      1. 7.5.1Power-Up Sequence
      2. 7.5.2Example Start-Up Routine
        1. 7.5.2.1Device Configuration
        2. 7.5.2.2PLL Configuration
        3. 7.5.2.3NCO Configuration
        4. 7.5.2.4Example Start-Up Sequence
    6. 7.6Register Map
      1. 7.6.1Register Descriptions
        1. 7.6.1.1 Register Name: config0 - Address: 0x00, Default: 0x049C
        2. 7.6.1.2 Register Name: config1 - Address: 0x01, Default: 0x050E
        3. 7.6.1.3 Register Name: config2 - Address: 0x02, Default: 0x7000
        4. 7.6.1.4 Register Name: config3 - Address: 0x03, Default: 0xF000
        5. 7.6.1.5 Register Name: config4 - Address: 0x04, Default: No RESET Value (WRITE TO CLEAR)
        6. 7.6.1.6 Register Name: config5 - Address: 0x05, Default: Setup and Power-Up Conditions Dependent (WRITE TO CLEAR)
        7. 7.6.1.7 Register Name: config6 - Address: 0x06, Default: No RESET Value (READ ONLY)
        8. 7.6.1.8 Register Name: config7 - Address: 0x07, Default: 0xFFFF
        9. 7.6.1.9 Register Name: config8 - Address: 0x08, Default: 0x0000 (CAUSES AUTO-SYNC)
        10. 7.6.1.10Register Name: config9 - Address: 0x09, Default: 0x8000
        11. 7.6.1.11Register Name: config10 - Address: 0x0A, Default: 0x0000
        12. 7.6.1.12Register Name: config11 - Address: 0x0B, Default: 0x0000
        13. 7.6.1.13Register Name: config12 - Address: 0x0C, Default: 0x0400
        14. 7.6.1.14Register Name: config13 - Address: 0x0D, Default: 0x0400
        15. 7.6.1.15Register Name: config14 - Address: 0x0E, Default: 0x0400
        16. 7.6.1.16Register Name: config15 - Address: 0x0F, Default: 0x0400
        17. 7.6.1.17Register Name: config16 - Address: 0x10, Default: 0x0000 (CAUSES AUTO-SYNC)
        18. 7.6.1.18Register Name: config17 - Address: 0x11, Default: 0x0000
        19. 7.6.1.19Register Name: config18 - Address: 0x12, Default: 0x0000 (CAUSES AUTO-SYNC)
        20. 7.6.1.20Register Name: config19 - Address: 0x13, Default: 0x0000
        21. 7.6.1.21Register Name: config20 - Address: 0x14, Default: 0x0000
        22. 7.6.1.22Register Name: config21 - Address: 0x15, Default: 0x0000
        23. 7.6.1.23Register name: config22 - Address: 0x16, Default: 0x0000
        24. 7.6.1.24Register Name: config23 - Address: 0x17, Default: 0x0000
        25. 7.6.1.25Register Name: config24 - Address: 0x18, Default: NA
        26. 7.6.1.26Register Name: config25 - Address: 0x19, Default: 0x0440
        27. 7.6.1.27Register Name: config26 - Address: 0x1A, Default: 0x0020
        28. 7.6.1.28Register Name: config27 - Address: 0x1B, Default: 0x0000
        29. 7.6.1.29Register Name: config28 - Address: 0x1C, Default: 0x0000
        30. 7.6.1.30Register Name: config29 - Address: 0x1D, Default: 0x0000
        31. 7.6.1.31Register Name: config30 - Address: 0x1E, Default: 0x1111
        32. 7.6.1.32Register Name: config31 - Address: 0x1F, Default: 0x1140
        33. 7.6.1.33Register Name: config32 - Address: 0x20, Default: 0x2400
        34. 7.6.1.34Register Name: config33 - Address: 0x21, Default: 0x0000
        35. 7.6.1.35Register Name: config34 - Address: 0x22, Default: 0x1B1B
        36. 7.6.1.36Register Name: config35 - Address: 0x23, Default: 0xFFFF
        37. 7.6.1.37Register Name: config36 - Address: 0x24, Default: 0x0000
        38. 7.6.1.38Register Name: config37 - Address: 0x25, Default: 0x7A7A
        39. 7.6.1.39Register Name: config38 - Address: 0x26, Default: 0xB6B6
        40. 7.6.1.40Register Name: config39 - Address: 0x27, Default: 0xEAEA
        41. 7.6.1.41Register Name: config40 - Address: 0x28, Default: 0x4545
        42. 7.6.1.42Register Name: config41 - Address: 0x29, Default: 0x1A1A
        43. 7.6.1.43Register Name: config42 - Address: 0x2A, Default: 0x1616
        44. 7.6.1.44Register Name: config43 - Address: 0x2B, Default: 0xAAAA
        45. 7.6.1.45Register Name: config44 - Address: 0x2C, Default: 0xC6C6
        46. 7.6.1.46Register Name: config45 - Address: 0x2D, Default: 0x0004
        47. 7.6.1.47Register Name: config46 - Address: 0x2E, Default: 0x0000
        48. 7.6.1.48Register Name: config47 - Address: 0x2F, Default: 0x0000
        49. 7.6.1.49Register Name: config48 - Address: 0x30, Default: 0x0000
        50. 7.6.1.50Register Name: version- Address: 0x7F, Default: 0x540C (READ ONLY)
  8. Application and Implementation
    1. 8.1Application Information
    2. 8.2Typical Applications
      1. 8.2.1IF Based LTE Transmitter
        1. 8.2.1.1Design Requirements
        2. 8.2.1.2Detailed Design Procedure
          1. 8.2.1.2.1Data Input Rate
          2. 8.2.1.2.2Interpolation
          3. 8.2.1.2.3LO Feedthrough and Sideband Correction
        3. 8.2.1.3Application Curves
      2. 8.2.2Direct Upconversion (Zero IF) LTE Transmitter
        1. 8.2.2.1Design Requirements
        2. 8.2.2.2Detailed Design Procedure
          1. 8.2.2.2.1Data Input Rate
          2. 8.2.2.2.2Interpolation
          3. 8.2.2.2.3LO Feedthrough and Sideband Correction
        3. 8.2.2.3Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Examples
    3. 10.3Assembly
  11. 11Device and Documentation Support
    1. 11.1Device Support
      1. 11.1.1Device Nomenclature
        1. 11.1.1.1Definition of Specifications
    2. 11.2Documentation Support
      1. 11.2.1Related Documentation
    3. 11.3Community Resources
    4. 11.4Trademarks
    5. 11.5Electrostatic Discharge Caution
    6. 11.6Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1Clarifications for DAC3482 Power Supply and Phase-Locked Loop Specification

1 Features

  • Very Low Power: 900 mW at 1.25 GSPS, Full Operating Conditions
  • Multi-DAC Synchronization
  • Selectable 2x, 4x, 8x, 16x Interpolation Filter
    • Stop-Band Attenuation > 90 dBc
  • Flexible On-Chip Complex Mixing
    • Fine Mixer with 32-Bit NCO
    • Power Saving Coarse Mixer: ± n×Fs/8
  • High Performance, Low Jitter Clock Multiplying PLL
  • Digital I and Q Correction
    • Gain, Phase, Offset, and Group Delay Correction
  • Digital Inverse Sinc Filter
  • Flexible LVDS Input Data Bus
    • Word- or Byte-Wide Interface
    • 8 Sample Input FIFO
    • Data Pattern Checker
    • Parity Check
  • Temperature Sensor
  • Differential Scalable Output: 10 mA to 30 mA
  • Multiple Package Options: 88-Pin 9x9mm WQFN-MR and 196-ball 12mmx12mm NFBGA (GREEN / Pb-Free)

2 Applications

  • Cellular Base Stations
  • Diversity Transmit
  • Wideband Communications

3 Description

The DAC3482 is a very low power, high dynamic range, dual-channel, 16-bit digital-to-analog converter (DAC) with a sample rate as high as 1.25 GSPS.

The device includes features that simplify the design of complex transmit architectures: 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. A complex mixer allows flexible carrier placement. A high-performance low jitter clock multiplier simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) enables complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications.

Digital data is input to the device through a flexible LVDS data bus with on-chip termination. Data can be input either word-wide or byte-wide. The device includes a FIFO, data pattern checker and parity test to ease the input interface. The interface also allows full synchronization of multiple devices.

The device is characterized for operation over the entire industrial temperature range of –40°C to 85°C and is available in a very-small 88-pin 9x9mm WQFN-MR package or 196-ball 12x12mm NFBGA package.

Very low power, small size, superior crosstalk, high dynamic range, and features of the DAC3482 make it an ideal fit for today’s communication systems.

Device Information(1)

PART NUMBERPACKAGEBODY SIZE (NOM)
DAC3482 WQFN-MR (88)9.00 mm x 9.00 mm
NFBGA (196)12.00 mm x 12.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Schematic

DAC3482 top_page_plot2_las748.gif