SNAS410F May 2008  – July 2016 DAC121S101QML-SP

PRODUCTION DATA. 

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5DAC121S101QML-SP Electrical Characteristics DC Parameters
    6. 6.6DAC121S101QML-SP Electrical Characteristics AC and Timing Characteristics
    7. 6.7DAC121S101QML Electrical Characteristics Radiation Electrical Characteristics
    8. 6.8DAC121S101QML-SP Electrical Characteristics Operating Life Test Delta Parameters TA at 25°C
    9. 6.9Typical Characteristics
  7. Detailed Description
    1. 7.1Overview
    2. 7.2Functional Block Diagram
    3. 7.3Feature Description
      1. 7.3.1DAC Section
      2. 7.3.2Resistor String
      3. 7.3.3Output Amplifier
      4. 7.3.4Power-On Reset
    4. 7.4Device Functional Modes
      1. 7.4.1Power-Down Modes
    5. 7.5Programming
      1. 7.5.1Serial Interface
      2. 7.5.2Input Shift Register
  8. Application and Implementation
    1. 8.1Application Information
      1. 8.1.1Bipolar Operation
      2. 8.1.2DSP and Microprocessor Interfacing
        1. 8.1.2.1ADSP-2101/ADSP2103 Interfacing
        2. 8.1.2.280C51/80L51 Interface
        3. 8.1.2.368HC11 Interface
        4. 8.1.2.4Microwire Interface
      3. 8.1.3Radiation Environments
        1. 8.1.3.1Total Ionizing Dose
          1. 8.1.3.1.1DAC121S101WGRQV 5962R0722601VZA
          2. 8.1.3.1.2DAC121S101WGRLV 5962R0722602VZA
        2. 8.1.3.2Single Event Latch-Up and Functional Interrupt
        3. 8.1.3.3Single Event Upset
    2. 8.2Typical Application
      1. 8.2.1Design Requirements
      2. 8.2.2Detailed Design Procedure
      3. 8.2.3Application Curve
  9. Power Supply Recommendations
    1. 9.1Using References as Power Supplies
      1. 9.1.1LM4050QML-SP
      2. 9.1.2LP3985
      3. 9.1.3LP2980-N
  10. 10Layout
    1. 10.1Layout Guidelines
    2. 10.2Layout Example
  11. 11Device and Documentation Support
    1. 11.1Device Support
      1. 11.1.1Development Support
      2. 11.1.2Device Nomenclature
        1. 11.1.2.1Specification Definitions
    2. 11.2Documentation Support
      1. 11.2.1Related Documentation
    3. 11.3Receiving Notification of Documentation Updates
    4. 11.4Community Resources
    5. 11.5Trademarks
    6. 11.6Electrostatic Discharge Caution
    7. 11.7Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1Engineering Samples

1 Features

  • 5962R07726
    • Total Ionizing Dose 100 krad(Si)
    • Single Event Latch-up Immune
      120 MeV-cm2/mg
    • Single Event Functional Interrupt Immune
      120 MeV-cm2/mg (See Radiation Report)
  • Ensured Monotonicity
  • Low Power Operation
  • Rail-to-Rail Voltage Output
  • Power-On Reset to Zero Volts Output
  • SYNC Interrupt Facility
  • Wide Power Supply Range (2.7 V to 5.5 V)
  • Small Packages
  • Power-Down Feature
  • Key Specifications
    • Resolution: 12 Bits
    • DNL: +0.21, –0.10 LSB (Typical)
    • Output Settling Time: 12.5 µs (Typical)
    • Zero Code Error: 2.1 mV (Typical)
    • Full-Scale Error: −0.04% FS (Typical)
    • Power Dissipation
      • Normal Mode: 0.52 mW (3.6 V) and 1.19 mW (5.5 V) Typical
      • Power-Down Mode: 0.014 µW (3.6 V) and 0.033 µW (5.5 V) Typical

2 Applications

  • Satellites
    • Altitude and Orbit Control
    • Precision Sensors
    • Motor Control
  • High Temperatures

3 Description

The DAC121S101QML-SP device is a full-featured, general-purpose, 12-bit voltage-output digital-to-analog converter (DAC) that can operate from a single 2.7-V to 5.5-V supply and consumes just
177 µA of current at 3.6 V. The on-chip output amplifier allows rail-to-rail output swing and the three-wire serial interface operates at clock rates up to
20 MHz over the specified supply voltage range and is compatible with standard SPI, QSPI, MICROWIRE, and DSP interfaces.

The supply voltage for the DAC121S101QML-SP serves as its voltage reference, providing the widest possible output dynamic range. A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a valid write to the device. A power-down feature reduces power consumption to less than a microWatt.

The low power consumption and small packages of the DAC121S101QML-SP make it an excellent choice for use in battery-operated equipment.

Device Information(1)

PART NUMBERGRADEPACKAGE
DAC121S101WGRQV 5962R0722601VZA 100 krad10-lead ceramic SOIC
DAC121S101WGRLV 5962R0722602VZA 100 krad ELDRS-Free10-lead ceramic SOIC
DAC121S101-MDR 5962R0722601V9A 100 kradDie
DAC121S101WGMPR Pre-Flight Engineering Prototype10-lead ceramic SOIC
DAC121S101CVAL Ceramic Evaluation Board10-lead ceramic SOIC
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Functional Block Diagram

DAC121S101QML-SP 30018003.gif

4 Revision History

Changes from E Revision (March 2013) to F Revision

  • Changed data sheet title DAC121S101QML 12-Bit Micro Power Digital-to-Analog Converter With Rail-to-Rail Output to DAC121S101QML-SP Radiation Hardened 12-Bit Micro Power Digital-to-Analog Converter With Rail-to-Rail OutputGo
  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.Go

Changes from D Revision (March 2013) to E Revision

  • Changed layout of National Data Sheet to TI formatGo