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CY29FCT520T

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8 位多级流水线寄存器

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数据表

CY29FCT520T

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数据表 立即订购

产品详情

Configuration Universal Bits (#) 8 Technology family FCT Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Standard CMOS Output type 3-State Clock frequency (MHz) 70 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 200 Features High speed (tpd 10-50ns), Partial power down (Ioff) Operating temperature range (°C) -40 to 85 Rating Catalog
Configuration Universal Bits (#) 8 Technology family FCT Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Standard CMOS Output type 3-State Clock frequency (MHz) 70 IOL (max) (mA) 64 IOH (max) (mA) -32 Supply current (max) (µA) 200 Features High speed (tpd 10-50ns), Partial power down (Ioff) Operating temperature range (°C) -40 to 85 Rating Catalog
SOIC (DW) 24 159.65 mm² 15.5 x 10.3
  • Function, Pinout, and Drive Compatible With FCT, F Logic, and AM29520
  • Reduced VOH (Typically = 3.3 V) Version of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Single- and Dual-Pipeline Operation Modes
  • Multiplexed Data Inputs and Outputs
  • CY29FCT520T
    • 64-mA Output Sink Current
      32-mA Output Source Current
  • CY29FCT520ATDMB, CY29FCT520BTDMB
    • 32-mA Output Sink Current
      12-mA Output Source Current
  • 3-State Outputs
  • Function, Pinout, and Drive Compatible With FCT, F Logic, and AM29520
  • Reduced VOH (Typically = 3.3 V) Version of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Single- and Dual-Pipeline Operation Modes
  • Multiplexed Data Inputs and Outputs
  • CY29FCT520T
    • 64-mA Output Sink Current
      32-mA Output Source Current
  • CY29FCT520ATDMB, CY29FCT520BTDMB
    • 32-mA Output Sink Current
      12-mA Output Source Current
  • 3-State Outputs

The CY29FCT520T is a multilevel 8-bit-wide pipeline register. The device consists of four registers, A1, A2, B1, and B2, which are configured by the instruction inputs I0, I1 as a single four-level pipeline or as two two-level pipelines. The contents of any register can be read at the multiplexed output at any time by using the multiplex-selection controls (S0 and S1).

The pipeline registers are positive-edge triggered, and data is shifted by the rising edge of the clock input. Instruction I = 0 selects the four-level pipeline mode. Instruction I = 1 selects the two-level B pipeline, while I = 2 selects the two-level A pipeline. I = 3 is the hold instruction; no shifting is performed by the clock in this mode.

In the two-level operation mode, data is shifted from level 1 to level 2 and new data is loaded into level 1.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The CY29FCT520T is a multilevel 8-bit-wide pipeline register. The device consists of four registers, A1, A2, B1, and B2, which are configured by the instruction inputs I0, I1 as a single four-level pipeline or as two two-level pipelines. The contents of any register can be read at the multiplexed output at any time by using the multiplex-selection controls (S0 and S1).

The pipeline registers are positive-edge triggered, and data is shifted by the rising edge of the clock input. Instruction I = 0 selects the four-level pipeline mode. Instruction I = 1 selects the two-level B pipeline, while I = 2 selects the two-level A pipeline. I = 3 is the hold instruction; no shifting is performed by the clock in this mode.

In the two-level operation mode, data is shifted from level 1 to level 2 and new data is loaded into level 1.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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其他器件和数据表

该数据表适用于 CY29FCT520T 和 CY29FCT520T-MIL

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技术文档

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类型 标题 下载最新的英语版本 日期
* 数据表 Multilevel Pipeline Register With 3-State Outputs 数据表 (Rev. C) 2001年 11月 2日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
选择指南 逻辑器件指南 2014 (Rev. AA) 最新英语版本 (Rev.AB) 2014年 11月 17日
选择指南 《高级总线接口逻辑器件选择指南》 英语版 2010年 7月 7日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
应用手册 选择正确的电平转换解决方案 (Rev. A) 英语版 (Rev.A) 2006年 3月 23日
应用手册 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
用户指南 CYFCT Parameter Measurement Information 2001年 4月 2日

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评估板

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用户指南: PDF | HTML
英语版 (Rev.B): PDF | HTML
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订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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