ZHCSBW6B December   2013  – May 2017 CSD19532Q5B

PRODUCTION DATA.  

  1. 1特性
  2. 2应用范围
  3. 3说明
  4. 4修订历史记录
  5. 5Specifications
    1. 5.1 Electrical Characteristics
    2. 5.2 Thermal Information
    3. 5.3 Typical MOSFET Characteristics
  6. 6器件和文档支持
    1. 6.1 接收文档更新通知
    2. 6.2 社区资源
    3. 6.3 商标
    4. 6.4 静电放电警告
    5. 6.5 Glossary
  7. 7机械、封装和可订购信息
    1. 7.1 Q5B 封装尺寸
    2. 7.2 建议 PCB 布局
    3. 7.3 建议模板布局
    4. 7.4 Q5B 卷带信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DNK|8
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Specifications

5.1 Electrical Characteristics

(TA = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 250 μA 100 V
IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 80 V 1 μA
IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = 20 V 100 nA
VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, ID = 250 μA 2.2 2.6 3.2 V
RDS(on) Drain-to-Source On Resistance VGS = 6 V, ID = 17 A 4.6 5.7 mΩ
VGS = 10 V, ID = 17 A 4 4.9 mΩ
gfs Transconductance VDS = 50 V, ID = 17 A 84 S
DYNAMIC CHARACTERISTICS
Ciss Input Capacitance VGS = 0 V, VDS = 50 V, ƒ = 1 MHz 3700 4810 pF
Coss Output Capacitance 706 918 pF
Crss Reverse Transfer Capacitance 14 18 pF
RG Series Gate Resistance 1.2 2.4 Ω
Qg Gate Charge Total (10 V) VDS = 50 V, ID = 17 A 48 62 nC
Qgd Gate Charge Gate to Drain 8.7 nC
Qgs Gate Charge Gate to Source 13 nC
Qg(th) Gate Charge at Vth 9.5 nC
Qoss Output Charge VDS = 50 V, VGS = 0 V 128 nC
td(on) Turn On Delay Time VDS = 50 V, VGS = 10 V,
IDS = 17 A, RG = 0 Ω		 7 ns
tr Rise Time 6 ns
td(off) Turn Off Delay Time 22 ns
tf Fall Time 6 ns
DIODE CHARACTERISTICS
VSD Diode Forward Voltage ISD = 17 A, VGS = 0 V 0.8 1 V
Qrr Reverse Recovery Charge VDS= 50 V, IF = 17 A,
di/dt = 300 A/μs		 249 nC
trr Reverse Recovery Time 80 ns

5.2 Thermal Information

(TA = 25°C unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJC Junction-to-Case Thermal Resistance(1) 0.8 °C/W
RθJA Junction-to-Ambient Thermal Resistance(1)(2) 50
(1) RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inches × 1.5-inches (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.

CSD19532Q5B M0137-01_LPS198.gif
Max RθJA = 50°C/W when mounted on 1 inch2 (6.45 cm2) of
2-oz. (0.071-mm thick) Cu.
CSD19532Q5B M0137-02_LPS198.gif
Max RθJA = 125°C/W when mounted on a minimum pad area of 2-oz. (0.071-mm thick) Cu.

5.3 Typical MOSFET Characteristics

(TA = 25°C unless otherwise stated)
CSD19532Q5B graph01p2_SLPS414.png
Figure 1. Transient Thermal Impedance
CSD19532Q5B graph02_SLPS414.png
Figure 2. Saturation Characteristics
CSD19532Q5B graph04_SLPS414.png
Figure 4. Gate Charge
CSD19532Q5B graph06_SLPS414.png
Figure 6. Threshold Voltage vs Temperature
CSD19532Q5B graph08_SLPS414.png
Figure 8. Normalized On-State Resistance vs Temperature
CSD19532Q5B graph10_SLPS414A.png
Figure 10. Maximum Safe Operating Area
CSD19532Q5B graph12p2_SLPS414.png
Figure 12. Maximum Drain Current vs Temperature
CSD19532Q5B graph03_SLPS414.png
Figure 3. Transfer Characteristics
CSD19532Q5B graph05_SLPS414.png
Figure 5. Capacitance
CSD19532Q5B graph07_SLPS414.png
Figure 7. On-State Resistance vs Gate-to-Source Voltage
CSD19532Q5B graph09_SLPS414.png
Figure 9. Typical Diode Forward Voltage
CSD19532Q5B graph11_SLPS414.png
Figure 11. Single Pulse Unclamped Inductive Switching