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Configurable & programmable logic ICs
Multivibrator one-shots

CD74HC4538-Q1

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汽车类高速 CMOS 逻辑双通道可重触发精密单稳多频振荡器

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CD74HC4538-Q1

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产品详情

Number of channels 2 Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Technology family HC Input type Standard CMOS Output type Push-Pull Supply current (µA) 80 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode, Retriggerable Operating temperature range (°C) -40 to 125 Rating Automotive
Number of channels 2 Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Technology family HC Input type Standard CMOS Output type Push-Pull Supply current (µA) 80 IOL (max) (mA) 5.2 IOH (max) (mA) -5.2 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode, Retriggerable Operating temperature range (°C) -40 to 125 Rating Automotive
SOIC (D) 16 59.4 mm² 9.9 x 6 TSSOP (PW) 16 32 mm² 5 x 6.4
  • Qualified for Automotive Applications
  • Retriggerable/Resettable Capability
  • Trigger and Reset Propagation Delays Independent of RX, CX
  • Triggering From the Leading or Trailing Edge
  • Q and Q Buffered Outputs Available
  • Separate Resets
  • Wide Range of Output Pulse Widths
  • Schmitt-Trigger Input on A and B Inputs
  • Retrigger Time Is Independent of CX
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . 15 LSTTL Loads
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • VCC Voltage = 2 V to 6 V
  • High Noise Immunity NIL or NIH = 30% of VCC, VCC = 5 V
  • Qualified for Automotive Applications
  • Retriggerable/Resettable Capability
  • Trigger and Reset Propagation Delays Independent of RX, CX
  • Triggering From the Leading or Trailing Edge
  • Q and Q Buffered Outputs Available
  • Separate Resets
  • Wide Range of Output Pulse Widths
  • Schmitt-Trigger Input on A and B Inputs
  • Retrigger Time Is Independent of CX
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . 15 LSTTL Loads
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • VCC Voltage = 2 V to 6 V
  • High Noise Immunity NIL or NIH = 30% of VCC, VCC = 5 V

The CD74HC4538 is a dual retriggerable/resettable precision monostable multivibrator for fixed-voltage timing applications. An external resistor (RX) and external capacitor (CX) control the timing and accuracy for the circuit. Adjustment of RX and CX provides a wide range of output pulse widths from the Q and Q\ terminals. The propagation delay from trigger input-to-output transition and the propagation delay from reset input-to-output transition are independent of RX and CX.

Leading-edge triggering (A) and trailing-edge triggering (B) inputs are provided for triggering from either edge of the input pulse. An unused A input should be tied to GND and an unused B input should be tied to VCC. On power up, the IC is reset. Unused resets and sections must be terminated. In normal operation, the circuit retriggers on the application of each new trigger pulse. To operate in the nontriggerable mode, Q is connected to B\ when leading-edge triggering (A) is used, or Q is connected to A when trailing-edge triggering (B) is used. The period τ can be calculated from τ = (0.7) RX, CX; RMIN is 5 kΩ. CMIN is 0 pF.

The CD74HC4538 is a dual retriggerable/resettable precision monostable multivibrator for fixed-voltage timing applications. An external resistor (RX) and external capacitor (CX) control the timing and accuracy for the circuit. Adjustment of RX and CX provides a wide range of output pulse widths from the Q and Q\ terminals. The propagation delay from trigger input-to-output transition and the propagation delay from reset input-to-output transition are independent of RX and CX.

Leading-edge triggering (A) and trailing-edge triggering (B) inputs are provided for triggering from either edge of the input pulse. An unused A input should be tied to GND and an unused B input should be tied to VCC. On power up, the IC is reset. Unused resets and sections must be terminated. In normal operation, the circuit retriggers on the application of each new trigger pulse. To operate in the nontriggerable mode, Q is connected to B\ when leading-edge triggering (A) is used, or Q is connected to A when trailing-edge triggering (B) is used. The period τ can be calculated from τ = (0.7) RX, CX; RMIN is 5 kΩ. CMIN is 0 pF.
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14-24-LOGIC-EVM — 采用 14 引脚至 24 引脚 D、DB、DGV、DW、DYY、NS 和 PW 封装的逻辑产品通用评估模块

14-24-LOGIC-EVM 评估模块 (EVM) 旨在支持采用 14 引脚至 24 引脚 D、DW、DB、NS、PW、DYY 或 DGV 封装的任何逻辑器件。

用户指南: PDF | HTML
英语版 (Rev.B): PDF | HTML
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仿真模型

CD74HC4538-Q1 PSpice Model

SCLM120.ZIP (36 KB) - PSpice Model
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封装 引脚 下载
SOIC (D) 16 查看选项
TSSOP (PW) 16 查看选项
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订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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