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SOIC (D) 16 59.4 mm² 9.9 x 6
  • Speed of Bipolar FCT, AS, and S, With Significantly Reduced Power Consumption
  • Digital Design Avoids Analog Compensation Errors
  • Easily Cascadable for Higher-Order Loops
  • Useful Frequency Range
    • DC to 110 MHz Typical (K CLK)
    • DC to 70 MHz Typical (I/D CLK)
  • Dynamically Variable Bandwidth
  • Very Narrow Bandwidth Attainable
  • Power-On Reset
  • Output Capability
    • Standard: XORPD OUT, ECPD OUT
    • Bus Driver: I/D OUT
  • SCR Latch-Up-Resistant CMOS Process and Circuit Design
  • Balanced Propagation Delays
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015

  • Speed of Bipolar FCT, AS, and S, With Significantly Reduced Power Consumption
  • Digital Design Avoids Analog Compensation Errors
  • Easily Cascadable for Higher-Order Loops
  • Useful Frequency Range
    • DC to 110 MHz Typical (K CLK)
    • DC to 70 MHz Typical (I/D CLK)
  • Dynamically Variable Bandwidth
  • Very Narrow Bandwidth Attainable
  • Power-On Reset
  • Output Capability
    • Standard: XORPD OUT, ECPD OUT
    • Bus Driver: I/D OUT
  • SCR Latch-Up-Resistant CMOS Process and Circuit Design
  • Balanced Propagation Delays
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015

The CD74ACT297 provides a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. This device contains all the necessary circuits, with the exception of the divide-by-N counter, to build first-order phase-locked loops as shown in Figure 1.

Both exclusive-OR phase detectors (XORPDs) and edge-controlled (ECPD) phase detectors are provided for maximum flexibility.

Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the designer to incorporate ripple cancellation or to cascade to higher-order phase-locked loops.

The length of the up/down K counter is digitally programmable according to the K-counter function table. With A, B, C, and D all low, the K counter is disabled. With A high and B, C, and D low, the K counter is only three stages long, which widens the bandwidth, or capture range, and shortens the lock time of the loop. When A, B, C, and D are programmed high, the K counter becomes 17 stages long, which narrows the bandwidth, or capture range, and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A-through-D inputs can maximize the overall performance of the digital phase-locked loop.

This device performs the classic first-order phase-locked-loop function without using analog components. The accuracy of the digital phase-locked loop (DPLL) is not affected by VCC and temperature variations, but depends solely on accuracies of the K clock (K CLK), increment/decrement clock (I/D CLK), and loop propagation delays. The I/D clock frequency and the divide-by-N modulos determine the center frequency of the DPLL. The center frequency is defined by the relationship fc = I/D clock/2N (Hz).

The CD74ACT297 provides a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. This device contains all the necessary circuits, with the exception of the divide-by-N counter, to build first-order phase-locked loops as shown in Figure 1.

Both exclusive-OR phase detectors (XORPDs) and edge-controlled (ECPD) phase detectors are provided for maximum flexibility.

Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the designer to incorporate ripple cancellation or to cascade to higher-order phase-locked loops.

The length of the up/down K counter is digitally programmable according to the K-counter function table. With A, B, C, and D all low, the K counter is disabled. With A high and B, C, and D low, the K counter is only three stages long, which widens the bandwidth, or capture range, and shortens the lock time of the loop. When A, B, C, and D are programmed high, the K counter becomes 17 stages long, which narrows the bandwidth, or capture range, and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A-through-D inputs can maximize the overall performance of the digital phase-locked loop.

This device performs the classic first-order phase-locked-loop function without using analog components. The accuracy of the digital phase-locked loop (DPLL) is not affected by VCC and temperature variations, but depends solely on accuracies of the K clock (K CLK), increment/decrement clock (I/D CLK), and loop propagation delays. The I/D clock frequency and the divide-by-N modulos determine the center frequency of the DPLL. The center frequency is defined by the relationship fc = I/D clock/2N (Hz).

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类型 标题 下载最新的英语版本 日期
* 数据表 Digital Phase-Locked Loop 数据表 (Rev. D) 2002年 6月 27日
应用手册 Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
选择指南 逻辑器件指南 2014 (Rev. AA) 最新英语版本 (Rev.AB) 2014年 11月 17日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
应用手册 选择正确的电平转换解决方案 (Rev. A) 英语版 (Rev.A) 2006年 3月 23日
应用手册 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
应用手册 TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
应用手册 CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
应用手册 使用逻辑器件进行设计 (Rev. C) 1997年 6月 1日
应用手册 Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996年 4月 1日

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英语版 (Rev.B): PDF | HTML
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订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

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