10.1 Layout Guidelines

It is important to pay special attention to the PCB layout. The following provides some guidelines:

• To obtain optimal performance, the decoupling capacitor from V_CC to V_(IN) and the output filter capacitors from OUT to V_SS should be placed as close as possible to the device, with short trace runs to both signal and V_SS pins. The V_SS pin should have short trace runs to the GND pin.
• All low-current V_SS connections should be kept separate from the high-current charge or discharge paths from the battery. Use a single-point ground technique incorporating both the small-signal ground path and the power ground path.
• The high-current charge paths into IN and from the OUT pins must be sized appropriately for the maximum charge current in order to avoid voltage drops in these traces.
• The device is packaged in a thermally enhanced MLP package. The package includes a thermal pad to provide an effective thermal contact between the device and the printed circuit board (PCB). Full PCB design guidelines for this package are provided in the application report entitled, QFN/SON PCB Attachment
  (TI Literature Number SLUA271).

10.2 Layout Example

Figure 13. Board Layout

10.3 Thermal Considerations

The bq24080-Q1 and bq24081-Q1 are packaged in a thermally enhanced MLP package. The package includes a thermal pad to provide an effective thermal contact between the device and the printed-circuit board (PCB). Full PCB design guidelines for this package are provided in the application report entitled, QFN/SON PCB Attachment (TI Literature Number SLUA271).

The most common measure of package thermal performance is thermal impedance (R_θJA) measured (or modeled) from the device junction to the air surrounding the package surface (ambient). The mathematical expression for R_θJA is:

Equation 11.

Where:

• T_J = device junction temperature
• T_A = ambient temperature
• P = device power dissipation

Factors that can greatly influence the measurement and calculation of R_θJA include:

• Orientation of the device (horizontal or vertical)
• Volume of the ambient air surrounding the device under test and airflow
• Whether other surfaces are in close proximity to the device being tested
• Use multiple 10–13 mil vias in the PowerPAD™ to copper ground plane.
• Avoid cutting the ground plane with a signal trace near the power IC.
• The PCB must be sized to have adequate surface area for heat dissipation.
• FR4 (figerglass) thickness should be minimized.

The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal Power FET. It can be calculated from the following equation:

Equation 12.

Due to the charge profile of Li-xx batteries, the maximum power dissipation is typically seen at the beginning of the charge cycle when the battery voltage is at its lowest. See Figure 6.