ZHCSE42C April 2015  – January 2017 ADS54J60

PRODUCTION DATA. 

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC Characteristics
    7. 7.7 Digital Characteristics
    8. 7.8 Timing Characteristics
    9. 7.9 Typical Characteristics
    10. 7.10Typical Characteristics: Contour
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1Analog Inputs
      2. 8.3.2DDC Block
        1. 8.3.2.1Decimate-by-2 Filter
        2. 8.3.2.2Decimate-by-4 Filter Using a Digital Mixer
        3. 8.3.2.3Decimate-by-4 Filter with IQ Outputs
      3. 8.3.3SYSREF Signal
        1. 8.3.3.1SYSREF Not Present (Subclass 0, 2)
      4. 8.3.4Overrange Indication
        1. 8.3.4.1Fast OVR
      5. 8.3.5Power-Down Mode
    4. 8.4Device Functional Modes
      1. 8.4.1Device Configuration
        1. 8.4.1.1Serial Interface
        2. 8.4.1.2Serial Register Write: Analog Bank
        3. 8.4.1.3Serial Register Readout: Analog Bank
        4. 8.4.1.4JESD Bank SPI Page Selection
        5. 8.4.1.5Serial Register Write: JESD Bank
          1. 8.4.1.5.1Individual Channel Programming
        6. 8.4.1.6Serial Register Readout: JESD Bank
      2. 8.4.2JESD204B Interface
        1. 8.4.2.1JESD204B Initial Lane Alignment (ILA)
        2. 8.4.2.2JESD204B Test Patterns
        3. 8.4.2.3JESD204B Frame
        4. 8.4.2.4JESD204B Frame
        5. 8.4.2.5JESD204B Frame Assembly with Decimation
          1. 8.4.2.5.1JESD Transmitter Interface
          2. 8.4.2.5.2Eye Diagram
    5. 8.5Register Maps
      1. 8.5.1Example Register Writes
      2. 8.5.2Register Descriptions
        1. 8.5.2.1General Registers
          1. 8.5.2.1.1Register 0h (address = 0h)
          2. 8.5.2.1.2Register 3h (address = 3h)
          3. 8.5.2.1.3Register 4h (address = 4h)
          4. 8.5.2.1.4Register 5h (address = 5h)
          5. 8.5.2.1.5Register 11h (address = 11h)
        2. 8.5.2.2Master Page (080h) Registers
          1. 8.5.2.2.1 Register 20h (address = 20h), Master Page (080h)
          2. 8.5.2.2.2 Register 21h (address = 21h), Master Page (080h)
          3. 8.5.2.2.3 Register 23h (address = 23h), Master Page (080h)
          4. 8.5.2.2.4 Register 24h (address = 24h), Master Page (080h)
          5. 8.5.2.2.5 Register 26h (address = 26h), Master Page (080h)
          6. 8.5.2.2.6 Register 4Fh (address = 4Fh), Master Page (080h)
          7. 8.5.2.2.7 Register 53h (address = 53h), Master Page (080h)
          8. 8.5.2.2.8 Register 54h (address = 54h), Master Page (080h)
          9. 8.5.2.2.9 Register 55h (address = 55h), Master Page (080h)
          10. 8.5.2.2.10Register 59h (address = 59h), Master Page (080h)
        3. 8.5.2.3ADC Page (0Fh) Register
          1. 8.5.2.3.1Register 5F (address = 5F), ADC Page (0Fh)
        4. 8.5.2.4Main Digital Page (6800h) Registers
          1. 8.5.2.4.1 Register 0h (address = 0h), Main Digital Page (6800h)
          2. 8.5.2.4.2 Register 41h (address = 41h), Main Digital Page (6800h)
          3. 8.5.2.4.3 Register 42h (address = 42h), Main Digital Page (6800h)
          4. 8.5.2.4.4 Register 43h (address = 43h), Main Digital Page (6800h)
          5. 8.5.2.4.5 Register 44h (address = 44h), Main Digital Page (6800h)
          6. 8.5.2.4.6 Register 4Bh (address = 4Bh), Main Digital Page (6800h)
          7. 8.5.2.4.7 Register 4Dh (address = 4Dh), Main Digital Page (6800h)
          8. 8.5.2.4.8 Register 4Eh (address = 4Eh), Main Digital Page (6800h)
          9. 8.5.2.4.9 Register 52h (address = 52h), Main Digital Page (6800h)
          10. 8.5.2.4.10Register 72h (address = 72h), Main Digital Page (6800h)
          11. 8.5.2.4.11Register ABh (address = ABh), Main Digital Page (6800h)
          12. 8.5.2.4.12Register ADh (address = ADh), Main Digital Page (6800h)
          13. 8.5.2.4.13Register F7h (address = F7h), Main Digital Page (6800h)
        5. 8.5.2.5JESD Digital Page (6900h) Registers
          1. 8.5.2.5.1 Register 0h (address = 0h), JESD Digital Page (6900h)
          2. 8.5.2.5.2 Register 1h (address = 1h), JESD Digital Page (6900h)
          3. 8.5.2.5.3 Register 2h (address = 2h), JESD Digital Page (6900h)
          4. 8.5.2.5.4 Register 3h (address = 3h), JESD Digital Page (6900h)
          5. 8.5.2.5.5 Register 5h (address = 5h), JESD Digital Page (6900h)
          6. 8.5.2.5.6 Register 6h (address = 6h), JESD Digital Page (6900h)
          7. 8.5.2.5.7 Register 7h (address = 7h), JESD Digital Page (6900h)
          8. 8.5.2.5.8 Register 16h (address = 16h), JESD Digital Page (6900h)
          9. 8.5.2.5.9 Register 31h (address = 31h), JESD Digital Page (6900h)
          10. 8.5.2.5.10Register 32h (address = 32h), JESD Digital Page (6900h)
        6. 8.5.2.6JESD Analog Page (6A00h) Register
          1. 8.5.2.6.1Register 12h-5h (address = 12h-5h), JESD Analog Page (6A00h)
          2. 8.5.2.6.2Register 16h (address = 16h), JESD Analog Page (6A00h)
          3. 8.5.2.6.3Register 17h (address = 17h), JESD Analog Page (6A00h)
          4. 8.5.2.6.4Register 1Ah (address = 1Ah), JESD Analog Page (6A00h)
          5. 8.5.2.6.5Register 1Bh (address = 1Bh), JESD Analog Page (6A00h)
  9. Application and Implementation
    1. 9.1Application Information
      1. 9.1.1Start-Up Sequence
      2. 9.1.2Hardware Reset
      3. 9.1.3SNR and Clock Jitter
    2. 9.2Typical Application
      1. 9.2.1Design Requirements
        1. 9.2.1.1Transformer-Coupled Circuits
      2. 9.2.2Detailed Design Procedure
      3. 9.2.3Application Curves
  10. 10Power Supply Recommendations
    1. 10.1Power Sequencing and Initialization
  11. 11Layout
    1. 11.1Layout Guidelines
    2. 11.2Layout Example
  12. 12器件和文档支持
    1. 12.1文档支持
      1. 12.1.1相关文档
    2. 12.2接收文档更新通知
    3. 12.3社区资源
    4. 12.4商标
    5. 12.5静电放电警告
    6. 12.6Glossary
  13. 13机械、封装和可订购信息

特性

  • 16 位分辨率、双通道、1GSPS 模数转换器 (ADC)
  • 噪底:–159dBFS/Hz
  • 频谱性能(–1dBFS 时,fIN = 170MHz):
    • 信噪比 (SNR):70dBFS
    • 噪声频谱密度 (NSD):–157dBFS/Hz
    • 无杂散动态范围 (SFDR):86dBc(包括交错音调)
    • SFDR:89dBc(不包括 HD2、HD3 和交错音调)
  • 频谱性能(–1dBFS 时,fIN = 350MHz):
    • SNR:67.5dBFS
    • NSD:–154.5dBFS/Hz
    • SFDR:75dBc
    • SFDR:85dBc(不包括 HD2、HD3 和交错音调)
  • 通道隔离:fIN = 170MHz 时为 100dBc
  • 输入满量程:1.9 VPP
  • 输入带宽 (3dB):1.2GHz
  • 片上抖动
  • 集成宽带数字下变频器 (DDC) 模块
  • 支持 JESD204B 子类 1 接口:
    • 10.0Gbps 时每个 ADC 2 条通道
    • 5.0Gbps 时每个 ADC 4 条通道
    • 支持多芯片同步
  • 功耗:1GSPS 时为 1.35W/通道
  • 封装:72 引脚超薄型四方扁平无引线 (10mm × 10mm)

应用

  • 雷达和天线阵列
  • 无线宽带
  • 电缆 CMTS、DOCSIS 3.1 接收器
  • 通信测试设备
  • 微波接收器
  • 软件定义无线电 (SDR)
  • 数字转换器
  • 医疗成像和诊断功能

说明

ADS54J60 是一款低功耗、高带宽 16 位、1.0GSPS 双通道模数转换器 (ADC)。该器件经设计具有高信噪比 (SNR),可提供 -159dBFS/Hz 的噪底,从而 协助应用在宽瞬时带宽内 实现最高动态范围。该器件支持 JESD204B 串行接口,数据传输速率高达 10Gbps,每个 ADC 可支持 2 或 4 条通道。已缓冲模拟输入在大大减少采样保持毛刺脉冲能量的同时,在宽频率范围内提供统一的输入阻抗。可选择将每个 ADC 通道连接至数字下变频器 (DDC) 模块。ADS54J60 以超低功耗在宽输入频率范围内提供出色的无杂散动态范围 (SFDR)。

JESD204B 接口减少了接口线路数,从而实现高系统集成度。内部锁相环 (PLL) 会将 ADC 采样时钟加倍,以获得串行化各通道的 16 位数据时所使用的位时钟。

器件信息

器件编号封装封装尺寸(标称值)
ADS54J60VQFNP (72)10.00mm x 10.00mm
  1. 要了解所有可用封装,请参见数据表末尾的可订购产品附录。

170MHz 输入信号的快速傅立叶变换 (FFT)
(SNR = 69.8dBFS;SFDR = 88dBc;
IL 毛刺 = 86dBc;非 HD2、HD3 毛刺 = 89dBc)

ADS54J60 D003_SBAS706.gif

修订历史记录

Changes from B Revision (August 2015) to C Revision

  • Changed 频谱性能特性要点的 最后一个 子要点中的 SFDR 值Go
  • Changed 器件信息表Go
  • Added Device Comparison TableGo
  • Added CDM row to ESD Ratings tableGo
  • Changed the minimum value for the input clock frequency in the Recommended Operating Conditions table Go
  • Added minimum value to the ADC sampling rate parameter in the Electrical Characteristics tableGo
  • Added 720 MHz test condition rows to SNR, NSD, SINAD, SFDR, HD2, HD3, Non HD2, HD3, THD, and SFDR_IL parameters of AC Characteristics tableGo
  • Changed typical specification of SFDR parameter in AC Characteristics tableGo
  • Changed Sample Timing, Aperture jitter parameter typical specification in Timing Characteristics sectionGo
  • Added the FOVR latency parameter to the Timing Characteristics tableGo
  • Added Figure 10Go
  • Added Typical Characteristics: Contour sectionGo
  • Changed Overview section Go
  • Changed Functional Block Diagram section: changed Control and SPI block and added dashed outline to FOVR tracesGo
  • Added Figure 60 and text reference to Analog Inputs sectionGo
  • Changed SYSREF Signal section: changed Table 4 and added last paragraphGo
  • Added SYSREF Not Present (Subclass 0, 2) sectionGo
  • Changed the number of clock cycles in the Fast OVR sectionGo
  • Changed Table 10 and Table 11Go
  • Changed Table 12 and Table 13Go
  • Deleted Lane Enable with Decimation subsection Go
  • Added the Program Summary of DDC Modes and JESD Link Configuration tableGo
  • Added Figure 83 to Register Maps sectionGo
  • Changed Table 15Go
  • Deleted register 39h, 3Ah, and 56h Go
  • Changed Example Register Writes sectionGo
  • Updated register descriptions Go
  • Added Table 51Go
  • Deleted row for bit 1 in Table 60 as bit 1 is included in last table row Go
  • Changed Table 65Go
  • Changed internal aperture jitter value in SNR and Clock Jitter sectionGo
  • Changed Figure 132Go
  • Changed Power Supply Recommendations section Go
  • Added the Power Sequencing and Initialization sectionGo
  • Added 文档支持接收文档更新通知部分Go

Changes from A Revision (May 2015) to B Revision

  • 已发布为量产数据Go