SBAS815A February 2017  – June 2017 ADS114S06 , ADS114S08

PRODUCTION DATA. 

  1. 1     Features
  2. 2     Applications
  3. 3     Description
  4. DeviceImages
    1. FunctionalBlock Diagram
  5. 4     Revision History
  6. 5     Device Family Comparison Table
  7. 6     Pin Configuration and Functions
    1. PinFunctions
  8. 7     Specifications
    1. 7.1Absolute Maximum Ratings
    2. 7.2ESD Ratings
    3. 7.3Recommended Operating Conditions
    4. 7.4Thermal Information
    5. 7.5Electrical Characteristics
    6. 7.6Timing Characteristics
    7. 7.7Switching Characteristics
    8. 7.8Typical Characteristics
  9. 8     Parameter Measurement Information
    1. 8.1Noise Performance
  10. 9     Detailed Description
    1. 9.1Overview
    2. 9.2Functional Block Diagram
    3. 9.3Feature Description
      1. 9.3.1 Multiplexer
      2. 9.3.2 Low-Noise Programmable Gain Amplifier
        1. 9.3.2.1PGA Input-Voltage Requirements
        2. 9.3.2.2PGA Rail Flags
        3. 9.3.2.3Bypassing the PGA
      3. 9.3.3 Voltage Reference
        1. 9.3.3.1Internal Reference
        2. 9.3.3.2External Reference
        3. 9.3.3.3Reference Buffers
      4. 9.3.4 Clock Source
      5. 9.3.5 Delta-Sigma Modulator
      6. 9.3.6 Digital Filter
        1. 9.3.6.1Low-Latency Filter
          1. 9.3.6.1.1Low-Latency Filter Frequency Response
          2. 9.3.6.1.2Data Conversion Time for the Low-Latency Filter
        2. 9.3.6.2Sinc3 Filter
          1. 9.3.6.2.1Sinc3 Filter Frequency Response
          2. 9.3.6.2.2Data Conversion Time for the Sinc3 Filter
        3. 9.3.6.3Note on Conversion Time
        4. 9.3.6.450-Hz and 60-Hz Line Cycle Rejection
        5. 9.3.6.5Global Chop Mode
      7. 9.3.7 Excitation Current Sources (IDACs)
      8. 9.3.8 Bias Voltage Generation
      9. 9.3.9 System Monitor
        1. 9.3.9.1Internal Temperature Sensor
        2. 9.3.9.2Power Supply Monitors
        3. 9.3.9.3Burn-Out Current Sources
      10. 9.3.10Status Register
        1. 9.3.10.1POR Flag
        2. 9.3.10.2RDY Flag
        3. 9.3.10.3PGA Output Voltage Rail Monitors
        4. 9.3.10.4Reference Monitor
      11. 9.3.11General-Purpose Inputs and Outputs (GPIOs)
      12. 9.3.12Low-Side Power Switch
      13. 9.3.13Cyclic Redundancy Check (CRC)
      14. 9.3.14Calibration
        1. 9.3.14.1Offset Calibration
        2. 9.3.14.2Gain Calibration
    4. 9.4Device Functional Modes
      1. 9.4.1Reset
        1. 9.4.1.1Power-On Reset
        2. 9.4.1.2RESET Pin
        3. 9.4.1.3Reset by Command
      2. 9.4.2Power-Down Mode
      3. 9.4.3Standby Mode
      4. 9.4.4Conversion Modes
        1. 9.4.4.1Continuous Conversion Mode
        2. 9.4.4.2Single-Shot Conversion Mode
        3. 9.4.4.3Programmable Conversion Delay
    5. 9.5Programming
      1. 9.5.1Serial Interface
        1. 9.5.1.1Chip Select (CS)
        2. 9.5.1.2Serial Clock (SCLK)
        3. 9.5.1.3Serial Data Input (DIN)
        4. 9.5.1.4Serial Data Output and Data Ready (DOUT/DRDY)
        5. 9.5.1.5Data Ready (DRDY)
        6. 9.5.1.6Timeout
      2. 9.5.2Data Format
      3. 9.5.3Commands
        1. 9.5.3.1 NOP
        2. 9.5.3.2 WAKEUP
        3. 9.5.3.3 POWERDOWN
        4. 9.5.3.4 RESET
        5. 9.5.3.5 START
        6. 9.5.3.6 STOP
        7. 9.5.3.7 SYOCAL
        8. 9.5.3.8 SYGCAL
        9. 9.5.3.9 SFOCAL
        10. 9.5.3.10RDATA
        11. 9.5.3.11RREG
        12. 9.5.3.12WREG
      4. 9.5.4Reading Data
        1. 9.5.4.1Read Data Direct
        2. 9.5.4.2Read Data by RDATA Command
        3. 9.5.4.3Sending Commands When Reading Data
      5. 9.5.5Interfacing with Multiple Devices
    6. 9.6Register Map
      1. 9.6.1Configuration Registers
        1. 9.6.1.1 Device ID Register (address = 00h) [reset = xxh]
          1. Table26. Device ID (ID) Register Field Descriptions
        2. 9.6.1.2 Device Status Register (address = 01h) [reset = 80h]
          1. Table27. Device Status (STATUS) Register Field Descriptions
        3. 9.6.1.3 Input Multiplexer Register (address = 02h) [reset = 01h]
          1. Table28. Input Multiplexer (INPMUX) Register Field Descriptions
        4. 9.6.1.4 Gain Setting Register (address = 03h) [reset = 00h]
          1. Table29. Gain Setting (PGA) Register Field Descriptions
        5. 9.6.1.5 Data Rate Register (address = 04h) [reset = 14h]
          1. Table30. Data Rate (DATARATE) Register Field Descriptions
        6. 9.6.1.6 Reference Control Register (address = 05h) [reset = 10h]
          1. Table31. Reference Control (REF) Register Field Descriptions
        7. 9.6.1.7 Excitation Current Register 1 (address = 06h) [reset = 00h]
          1. Table32. Excitation Current Register 1 (IDACMAG) Register Field Descriptions
        8. 9.6.1.8 Excitation Current Register 2 (address = 07h) [reset = FFh]
          1. Table33. Excitation Current Register 2 (IDACMUX) Register Field Descriptions
        9. 9.6.1.9 Sensor Biasing Register (address = 08h) [reset = 00h]
          1. Table34. Sensor Biasing (VBIAS) Register Field Descriptions
        10. 9.6.1.10System Control Register (address = 09h) [reset = 10h]
          1. Table35. System Control (SYS) Register Field Descriptions
        11. 9.6.1.11Reserved Register (address = 0Ah) [reset = 00h]
          1. Table36. Reserved Register Field Descriptions
        12. 9.6.1.12Offset Calibration Register 1 (address = 0Bh) [reset = 00h]
          1. Table37. Offset Calibration Register 1 (OFCAL0) Register Field Descriptions
        13. 9.6.1.13Offset Calibration Register 2 (address = 0Ch) [reset = 00h]
          1. Table38. Offset Calibration Register 2 (OFCAL1) Register Field Descriptions
        14. 9.6.1.14Reserved Register (address = 0Dh) [reset = 00h]
          1. Table39. Reserved Register Field Descriptions
        15. 9.6.1.15Gain Calibration Register 1 (address = 0Eh) [reset = 00h]
          1. Table40. Gain Calibration Register 1 (FSCAL0) Field Descriptions
        16. 9.6.1.16Gain Calibration Register 2 (address = 0Fh) [reset = 40h]
          1. Table41. Gain Calibration Register 2 (FSCAL1) Field Descriptions
        17. 9.6.1.17GPIO Data Register (address = 10h) [reset = 00h]
          1. Table42. GPIO Data (GPIODAT) Register Field Descriptions
        18. 9.6.1.18GPIO Configuration Register (address = 11h) [reset = 00h]
          1. Table43. GPIO Configuration (GPIOCON) Register Field Descriptions
  11. 10    Application and Implementation
    1. 10.1Application Information
      1. 10.1.1Serial Interface Connections
      2. 10.1.2Analog Input Filtering
      3. 10.1.3External Reference and Ratiometric Measurements
      4. 10.1.4Establishing a Proper Input Voltage
      5. 10.1.5Unused Inputs and Outputs
      6. 10.1.6Pseudo Code Example
    2. 10.2Typical Application
      1. 10.2.1Design Requirements
      2. 10.2.2Detailed Design Procedure
        1. 10.2.2.1Register Settings
      3. 10.2.3Application Curves
    3. 10.3Do's and Don'ts
  12. 11    Power Supply Recommendations
    1. 11.1Power Supplies
    2. 11.2Power-Supply Sequencing
    3. 11.3Power-On Reset
    4. 11.4Power-Supply Decoupling
  13. 12    Layout
    1. 12.1Layout Guidelines
    2. 12.2Layout Example
  14. 13    Device and Documentation Support
    1. 13.1Device Support
      1. 13.1.1Development Support
    2. 13.2Documentation Support
      1. 13.2.1Related Documentation
    3. 13.3Related Links
    4. 13.4Receiving Notification of Documentation Updates
    5. 13.5Community Resources
    6. 13.6Trademarks
    7. 13.7Electrostatic Discharge Caution
    8. 13.8Glossary
  15. 14    Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RHB|32
  • PBS|32
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