ZHCSFG2C May 2016  – December 2016 ADC32RF45

PRODUCTION DATA. 

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1Absolute Maximum Ratings
    2. 6.2ESD Ratings
    3. 6.3Recommended Operating Conditions
    4. 6.4Thermal Information
    5. 6.5Electrical Characteristics
    6. 6.6AC Performance Characteristics
    7. 6.7Digital Requirements
    8. 6.8Timing Requirements
    9. 6.9Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1Input Clock Diagram
  8. Detailed Description
    1. 8.1Overview
    2. 8.2Functional Block Diagram
    3. 8.3Feature Description
      1. 8.3.1 Analog Inputs
        1. 8.3.1.1Input Clamp Circuit
      2. 8.3.2 Clock Input
      3. 8.3.3 SYSREF Input
        1. 8.3.3.1Using SYSREF
        2. 8.3.3.2Frequency of the SYSREF Signal
      4. 8.3.4 DDC Block
        1. 8.3.4.1Operating Mode: Receiver
        2. 8.3.4.2Operating Mode: Wide-Bandwidth Observation Receiver
        3. 8.3.4.3Decimation Filters
          1. 8.3.4.3.1 Divide-by-4
          2. 8.3.4.3.2 Divide-by-6
          3. 8.3.4.3.3 Divide-by-8
          4. 8.3.4.3.4 Divide-by-9
          5. 8.3.4.3.5 Divide-by-10
          6. 8.3.4.3.6 Divide-by-12
          7. 8.3.4.3.7 Divide-by-16
          8. 8.3.4.3.8 Divide-by-18
          9. 8.3.4.3.9 Divide-by-20
          10. 8.3.4.3.10Divide-by-24
          11. 8.3.4.3.11Divide-by-32
          12. 8.3.4.3.12Latency with Decimation Options
        4. 8.3.4.4Digital Multiplexer (MUX)
        5. 8.3.4.5Numerically-Controlled Oscillators (NCOs) and Mixers
      5. 8.3.5 NCO Switching
      6. 8.3.6 SerDes Transmitter Interface
      7. 8.3.7 Eye Diagrams
      8. 8.3.8 Alarm Outputs: Power Detectors for AGC Support
        1. 8.3.8.1Absolute Peak Power Detector
        2. 8.3.8.2Crossing Detector
        3. 8.3.8.3RMS Power Detector
        4. 8.3.8.4GPIO AGC MUX
      9. 8.3.9 Power-Down Mode
      10. 8.3.10ADC Test Pattern
        1. 8.3.10.1Digital Block
        2. 8.3.10.2Transport Layer
        3. 8.3.10.3Link Layer
    4. 8.4Device Functional Modes
      1. 8.4.1Device Configuration
      2. 8.4.2JESD204B Interface
        1. 8.4.2.1JESD204B Initial Lane Alignment (ILA)
        2. 8.4.2.2JESD204B Frame Assembly
        3. 8.4.2.3JESD204B Frame Assembly in Bypass Mode
        4. 8.4.2.4JESD204B Frame Assembly with Decimation (Single-Band DDC): Complex Output
        5. 8.4.2.5JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output
        6. 8.4.2.6JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output
        7. 8.4.2.7JESD204B Frame Assembly with Decimation (Dual-Band DDC): Complex Output
        8. 8.4.2.8JESD204B Frame Assembly with Decimation (Dual-Band DDC): Real Output
      3. 8.4.3Serial Interface
        1. 8.4.3.1Serial Register Write: Analog Bank
        2. 8.4.3.2Serial Register Readout: Analog Bank
        3. 8.4.3.3Serial Register Write: Digital Bank
        4. 8.4.3.4Serial Register Readout: Digital Bank
        5. 8.4.3.5Serial Register Write: Decimation Filter and Power Detector Pages
    5. 8.5Register Maps
      1. 8.5.1 Example Register Writes
      2. 8.5.2 Register Descriptions
        1. 8.5.2.1General Registers
          1. 8.5.2.1.1Register 000h (address = 000h), General Registers
          2. 8.5.2.1.2Register 002h (address = 002h), General Registers
          3. 8.5.2.1.3Register 003h (address = 003h), General Registers
          4. 8.5.2.1.4Register 004h (address = 004h), General Registers
          5. 8.5.2.1.5Register 010h (address = 010h), General Registers
          6. 8.5.2.1.6Register 011h (address = 011h), General Registers
          7. 8.5.2.1.7Register 012h (address = 012h), General Registers
      3. 8.5.3 Master Page (M = 0)
        1. 8.5.3.1Register 020h (address = 020h), Master Page
        2. 8.5.3.2Register 032h (address = 032h), Master Page
        3. 8.5.3.3Register 039h (address = 039h), Master Page
        4. 8.5.3.4Register 03Ch (address = 03Ch), Master Page
        5. 8.5.3.5Register 05Ah (address = 05Ah), Master Page
        6. 8.5.3.6Register 03Dh (address = 3Dh), Master Page
        7. 8.5.3.7Register 057h (address = 057h), Master Page
        8. 8.5.3.8Register 058h (address = 058h), Master Page
      4. 8.5.4 ADC Page (FFh, M = 0)
        1. 8.5.4.1Register 03Fh (address = 03Fh), ADC Page
        2. 8.5.4.2Register 042h (address = 042h), ADC Page
      5. 8.5.5 Digital Function Page (610000h, M = 1 for Channel A and 610100h, M = 1 for Channel B)
        1. 8.5.5.1Register A6h (address = 0A6h), Digital Function Page
      6. 8.5.6 Offset Corr Page Channel A (610000h, M = 1)
        1. 8.5.6.1Register 034h (address = 034h), Offset Corr Page Channel A
        2. 8.5.6.2Register 068h (address = 068h), Offset Corr Page Channel A
      7. 8.5.7 Offset Corr Page Channel B (610000h, M = 1)
        1. 8.5.7.1Register 068h (address = 068h), Offset Corr Page Channel B
      8. 8.5.8 Digital Gain Page (610005h, M = 1 for Channel A and 610105h, M = 1 for Channel B)
        1. 8.5.8.1Register 0A6h (address = 0A6h), Digital Gain Page
      9. 8.5.9 Main Digital Page Channel A (680000h, M = 1)
        1. 8.5.9.1Register 000h (address = 000h), Main Digital Page Channel A
        2. 8.5.9.2Register 0A2h (address = 0A2h), Main Digital Page Channel A
      10. 8.5.10Main Digital Page Channel B (680001h, M = 1)
        1. 8.5.10.1Register 000h (address = 000h), Main Digital Page Channel B
        2. 8.5.10.2Register 0A2h (address = 0A2h), Main Digital Page Channel B
      11. 8.5.11JESD Digital Page (6900h, M = 1)
        1. 8.5.11.1 Register 001h (address = 001h), JESD Digital Page
        2. 8.5.11.2 Register 002h (address = 002h ), JESD Digital Page
        3. 8.5.11.3 Register 003h (address = 003h), JESD Digital Page
        4. 8.5.11.4 Register 004h (address = 004h), JESD Digital Page
        5. 8.5.11.5 Register 006h (address = 006h), JESD Digital Page
        6. 8.5.11.6 Register 007h (address = 007h), JESD Digital Page
        7. 8.5.11.7 Register 016h (address = 016h), JESD Digital Page
        8. 8.5.11.8 Register 017h (address = 017h), JESD Digital Page
        9. 8.5.11.9 Register 032h-035h (address = 032h-035h), JESD Digital Page
        10. 8.5.11.10Register 036h (address = 036h), JESD Digital Page
        11. 8.5.11.11Register 037h (address = 037h), JESD Digital Page
        12. 8.5.11.12Register 03Eh (address = 03Eh), JESD Digital Page
      12. 8.5.12Decimation Filter Page
        1. 8.5.12.1 Register 000h (address = 000h), Decimation Filter Page
        2. 8.5.12.2 Register 001h (address = 001h), Decimation Filter Page
        3. 8.5.12.3 Register 002h (address = 2h), Decimation Filter Page
        4. 8.5.12.4 Register 005h (address = 005h), Decimation Filter Page
        5. 8.5.12.5 Register 006h (address = 006h), Decimation Filter Page
        6. 8.5.12.6 Register 007h (address = 007h), Decimation Filter Page
        7. 8.5.12.7 Register 008h (address = 008h), Decimation Filter Page
        8. 8.5.12.8 Register 009h (address = 009h), Decimation Filter Page
        9. 8.5.12.9 Register 00Ah (address = 00Ah), Decimation Filter Page
        10. 8.5.12.10Register 00Bh (address = 00Bh), Decimation Filter Page
        11. 8.5.12.11Register 00Ch (address = 00Ch), Decimation Filter Page
        12. 8.5.12.12Register 00Dh (address = 00Dh), Decimation Filter Page
        13. 8.5.12.13Register 00Eh (address = 00Eh), Decimation Filter Page
        14. 8.5.12.14Register 00Fh (address = 00Fh), Decimation Filter Page
        15. 8.5.12.15Register 010h (address = 010h), Decimation Filter Page
        16. 8.5.12.16Register 011h (address = 011h), Decimation Filter Page
        17. 8.5.12.17Register 014h (address = 014h), Decimation Filter Page
        18. 8.5.12.18Register 016h (address = 016h), Decimation Filter Page
        19. 8.5.12.19Register 01Eh (address = 01Eh), Decimation Filter Page
        20. 8.5.12.20Register 01Fh (address = 01Fh), Decimation Filter Page
        21. 8.5.12.21Register 033h-036h (address = 033h-036h), Decimation Filter Page
        22. 8.5.12.22Register 037h (address = 037h), Decimation Filter Page
        23. 8.5.12.23Register 03Ah (address = 03Ah), Decimation Filter Page
      13. 8.5.13Power Detector Page
        1. 8.5.13.1 Register 000h (address = 000h), Power Detector Page
        2. 8.5.13.2 Register 001h-002h (address = 001h-002h), Power Detector Page
        3. 8.5.13.3 Register 003h (address = 003h), Power Detector Page
        4. 8.5.13.4 Register 007h-00Ah (address = 007h-00Ah), Power Detector Page
        5. 8.5.13.5 Register 00Bh-00Ch (address = 00Bh-00Ch), Power Detector Page
        6. 8.5.13.6 Register 00Dh (address = 00Dh), Power Detector Page
        7. 8.5.13.7 Register 00Eh (address = 00Eh), Power Detector Page
        8. 8.5.13.8 Register 00Fh, 010h-012h, and 016h-019h (address = 00Fh, 010h-012h, and 016h-019h), Power Detector Page
        9. 8.5.13.9 Register 013h-01Ah (address = 013h-01Ah), Power Detector Page
        10. 8.5.13.10Register 01Dh-01Eh (address = 01Dh-01Eh), Power Detector Page
        11. 8.5.13.11Register 020h (address = 020h), Power Detector Page
        12. 8.5.13.12Register 021h (address = 021h), Power Detector Page
        13. 8.5.13.13Register 022h-025h (address = 022h-025h), Power Detector Page
        14. 8.5.13.14Register 027h (address = 027h), Power Detector Page
        15. 8.5.13.15Register 02Bh (address = 02Bh), Power Detector Page
        16. 8.5.13.16Register 032h-035h (address = 032h-035h), Power Detector Page
        17. 8.5.13.17Register 037h (address = 037h), Power Detector Page
        18. 8.5.13.18Register 038h (address = 038h), Power Detector Page
  9. Application and Implementation
    1. 9.1Application Information
      1. 9.1.1Start-Up Sequence
      2. 9.1.2Hardware Reset
      3. 9.1.3SNR and Clock Jitter
        1. 9.1.3.1External Clock Phase Noise Consideration
      4. 9.1.4Power Consumption in Different Modes
      5. 9.1.5Using DC Coupling in the ADC32RF45
        1. 9.1.5.1Bypassing the Offset Corrector Block
          1. 9.1.5.1.1Effect of Temperature
    2. 9.2Typical Application
      1. 9.2.1Design Requirements
        1. 9.2.1.1Transformer-Coupled Circuits
      2. 9.2.2Detailed Design Procedure
      3. 9.2.3Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1Layout Guidelines
    2. 11.2Layout Example
  12. 12器件和文档支持
    1. 12.1文档支持
      1. 12.1.1相关文档 
    2. 12.2接收文档更新通知
    3. 12.3社区资源
    4. 12.4商标
    5. 12.5静电放电警告
    6. 12.6Glossary
  13. 13机械、封装和可订购信息

特性

  • 14 位双通道 3.0GSPS 模数转换器
  • 噪底:–155dBFS/Hz
  • RF 输入支持的频率最高达 4.0GHz
  • 孔径抖动:90fs
  • 通道隔离:95dB(fIN = 1.8GHz 时)
  • 频谱性能(fIN = 900MHz,–2dBFS):
    • 信噪比 (SNR):60.9dBFS
    • 无杂散动态范围 (SFDR):67dBc(HD2、HD3)
    • SFDR:77dBc(最严重毛刺)
  • 频谱性能(fIN = 1.78GHz,–2dBFS):
    • SNR:58.8dBFS
    • SFDR:66Bc(HD2、HD3)
    • SFDR:75dBc(最严重毛刺)
  • 片上数字下变频器:
    • 最多 4 个 DDC(双频带模式)
    • 每个 DDC 最多 3 个独立的数控振荡器 (NCO)
  • 片上输入钳位,用于过压保护
  • 带有报警引脚的可编程片上功率检测器,支持自动增益控制 (AGC)
  • 片上抖动
  • 片上输入端接电阻
  • 输入满量程:1.35 VPP
  • 支持多芯片同步
  • JESD204B 接口:
    • 基于子类 1 的确定性延迟
    • 12.5Gbps 时每个通道具有 4 条信道
  • 功耗:3.0GSPS 时为 3.2W/通道
  • 72 引脚超薄型四方扁平无引线 (VQFN) 封装 (10mm × 10mm)

应用

  • 多频带、多模式 2G、3G、4G 蜂窝接收器
  • 相控阵列雷达
  • 电子对抗战
  • 线缆基础设施
  • 无线宽带
  • 高速数字转换器
  • 软件定义无线电
  • 通信测试设备
  • 微波和毫米波接收器

说明

ADC32RF45器件是一款 14 位 3.0GSPS 双通道模数转换器 (ADC),支持输入频率高达 4GHz 及以上的射频 (RF) 采样。ADC32RF45设计旨在追求高信噪比 (SNR),其在宽输入频率范围内兼具 –155dBFS/Hz 的噪声频谱密度与动态范围,并且可提供通道隔离。经缓冲的模拟输入配有片上端接电阻,可在较宽频率范围内提供统一输入阻抗并最大程度地降低采样和保持毛刺脉冲能量。

每个 ADC 通道均可连接到一个双频带数字下变频器 (DDC),每个 DDC 最多连接三个独立的 16 位数控振荡器 (NCO) 用于相位相干跳频。此外,ADC 还配有前端峰值和 RMS 功率检测器及报警功能,用以支持外部自动增益控制 (AGC) 算法。

ADC32RF45支持 JESD204B 串行接口。该接口具有基于子类 1 的确定性延迟,数据传输速率高达 12.5Gbps,每个 ADC 最多四条信道。该器件采用 72 引脚 VQFN 封装 (10mm × 10mm),支持工业级温度范围(-40℃ 到 +85°C)。

器件信息(1)

器件型号封装封装尺寸(标称值)
ADC32RF45VQFN (72)10.00mm x 10.00mm
  1. 要了解所有可用封装,请见数据表末尾的可订购产品附录。

简化框图

ADC32RF45 frontpage_sbas747.gif

修订历史记录

Changes from B Revision (June 2016) to C Revision

  • 已发布为“量产数据”Go