产品详情

Sample rate (max) (Msps) 65 Resolution (Bits) 10 Number of input channels 2 Interface type Parallel CMOS, TTL Analog input BW (MHz) 250 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 370 Architecture Pipeline SNR (dB) 61 ENOB (bit) 9.8 SFDR (dB) 86 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 65 Resolution (Bits) 10 Number of input channels 2 Interface type Parallel CMOS, TTL Analog input BW (MHz) 250 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 370 Architecture Pipeline SNR (dB) 61 ENOB (bit) 9.8 SFDR (dB) 86 Operating temperature range (°C) -40 to 85 Input buffer No
TQFP (PAG) 64 144 mm² 12 x 12
  • Single +3.3V Supply Operation
  • Internal Sample-and-Hold
  • Internal Reference
  • Outputs 2.4V to 3.6V Compatible
  • Power Down Mode
  • Duty Cycle Stabilizer
  • Multiplexed Output Mode

Key Specifications

  • Resolution 10 Bits
  • DNL ±0.16 LSB (typ)
  • SNR (fIN = 10 MHz) 61 dB (typ)
  • SFDR (fIN = 10 MHz) 85 dB (typ)
  • Data Latency 7 Clock Cycles
  • Power Consumption
    • Operating 370 mW (typ)
    • Power Down Mode 36 mW (typ)

All trademarks are the property of their respective owners.

  • Single +3.3V Supply Operation
  • Internal Sample-and-Hold
  • Internal Reference
  • Outputs 2.4V to 3.6V Compatible
  • Power Down Mode
  • Duty Cycle Stabilizer
  • Multiplexed Output Mode

Key Specifications

  • Resolution 10 Bits
  • DNL ±0.16 LSB (typ)
  • SNR (fIN = 10 MHz) 61 dB (typ)
  • SFDR (fIN = 10 MHz) 85 dB (typ)
  • Data Latency 7 Clock Cycles
  • Power Consumption
    • Operating 370 mW (typ)
    • Power Down Mode 36 mW (typ)

All trademarks are the property of their respective owners.

The ADC10DL065 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 65 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption while providing excellent dynamic performance and a 250 MHz Full Power Bandwidth. Operating on a single +3.3V power supply, the ADC10DL065 achieves 9.8 effective bits at nyquist and consumes just 370 mW at 65 MSPS, including the reference current. The Power Down feature reduces power consumption to 36 mW.

The differential inputs provide a full scale differential input swing equal to 2 times VREF with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. The digital outputs from the two ADC's are available on a single multiplexed 10-bit bus or on separate buses. Duty cycle stabilization and output data format are selectable using a quad state function pin. The output data can be set for offset binary or two's complement.

To ease interfacing to lower voltage systems, the digital output driver power pins of the ADC10DL065 can be connected to a separate supply voltage in the range of 2.4V to the analog supply voltage. This device is available in the 64-lead TQFP package and will operate over the industrial temperature range of −40°C to +85°C. An evaluation board is available to ease the evaluation process.

The ADC10DL065 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 65 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption while providing excellent dynamic performance and a 250 MHz Full Power Bandwidth. Operating on a single +3.3V power supply, the ADC10DL065 achieves 9.8 effective bits at nyquist and consumes just 370 mW at 65 MSPS, including the reference current. The Power Down feature reduces power consumption to 36 mW.

The differential inputs provide a full scale differential input swing equal to 2 times VREF with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. The digital outputs from the two ADC's are available on a single multiplexed 10-bit bus or on separate buses. Duty cycle stabilization and output data format are selectable using a quad state function pin. The output data can be set for offset binary or two's complement.

To ease interfacing to lower voltage systems, the digital output driver power pins of the ADC10DL065 can be connected to a separate supply voltage in the range of 2.4V to the analog supply voltage. This device is available in the 64-lead TQFP package and will operate over the industrial temperature range of −40°C to +85°C. An evaluation board is available to ease the evaluation process.

下载 观看带字幕的视频 视频

技术文档

star =有关此产品的 TI 精选热门文档
未找到结果。请清除搜索并重试。
查看全部 3
类型 标题 下载最新的英语版本 日期
* 数据表 ADC10DL065 Dual 10-Bit, 65 MSPS, 3.3V, 370mW A/D Converter 数据表 (Rev. B) 2013年 4月 18日
用户指南 ADC10DL065/ADC12DL040/ADC12DL065 Instruction Manual 2012年 2月 21日
应用手册 Understanding High-Speed Signals, Clocks, and Data Capture 2005年 10月 18日

设计和开发

如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。

模拟工具

PSPICE-FOR-TI — 适用于 TI 设计和模拟工具的 PSpice®

PSpice® for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence® 的模拟分析引擎。PSpice for TI 可免费使用,包括业内超大的模型库之一,涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助 PSpice for TI 的设计和仿真环境及其内置的模型库,您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案,然后再进行布局和制造,可缩短产品上市时间并降低开发成本。

在 PSpice for TI 设计和仿真工具中,您可以搜索 TI (...)
封装 引脚 下载
TQFP (PAG) 64 查看选项

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

支持和培训

视频