产品详情

Sample rate (max) (Msps) 1000, 2000 Resolution (Bits) 10 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2800 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 2770 Architecture Folding Interpolating SNR (dB) 57 ENOB (bit) 9.1 SFDR (dB) 70 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 1000, 2000 Resolution (Bits) 10 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2800 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 2770 Architecture Folding Interpolating SNR (dB) 57 ENOB (bit) 9.1 SFDR (dB) 70 Operating temperature range (°C) -40 to 85 Input buffer Yes
PBGA (NXA) 292 729 mm² 27 x 27
  • Excellent Accuracy and Dynamic Performance
  • Pin Compatible with ADC12D1000/1600/1800
  • Low Power Consumption, Further Reduced at Lower Fs
  • Internally Terminated, Buffered, Differential Analog Inputs
  • R/W SPI Interface for Extended Control Mode
  • Dual-Edge Sampling Mode, in Which the I- and Q-channels Sample One Input at Twice the Sampling Clock Rate
  • Test Patterns at Output for System Debug
  • Programmable 15-bit Gain and 12-bit Plus Sign Offset
  • Programmable tAD Adjust Feature
  • 1:1 Non-demuxed or 1:2 Demuxed LVDS Outputs
  • AutoSync Feature for Multi-Chip Systems
  • Single 1.9V ± 0.1V Power Supply
  • 292-Ball BGA Package (27mm x 27mm x 2.4mm with 1.27mm Ball-Pitch); No Heat Sink Required

All trademarks are the property of their respective owners.

  • Excellent Accuracy and Dynamic Performance
  • Pin Compatible with ADC12D1000/1600/1800
  • Low Power Consumption, Further Reduced at Lower Fs
  • Internally Terminated, Buffered, Differential Analog Inputs
  • R/W SPI Interface for Extended Control Mode
  • Dual-Edge Sampling Mode, in Which the I- and Q-channels Sample One Input at Twice the Sampling Clock Rate
  • Test Patterns at Output for System Debug
  • Programmable 15-bit Gain and 12-bit Plus Sign Offset
  • Programmable tAD Adjust Feature
  • 1:1 Non-demuxed or 1:2 Demuxed LVDS Outputs
  • AutoSync Feature for Multi-Chip Systems
  • Single 1.9V ± 0.1V Power Supply
  • 292-Ball BGA Package (27mm x 27mm x 2.4mm with 1.27mm Ball-Pitch); No Heat Sink Required

All trademarks are the property of their respective owners.

The ADC10D1000/1500 is the latest advance in TI's Ultra-High-Speed ADC family. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution for dual channels at sampling rates of up to 1.0/1.5 GSPS (Non-DES Mode) or for a single channel up to 2.0/3.0 GSPS (DES Mode). The ADC10D1000/1500 achieves excellent accuracy and dynamic performance while dissipating less than 2.8/3.6 Watts. The product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40°C to +85°C.

The ADC10D1000/1500 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. An expanded feature set includes AutoSync for multi-chip synchronization, 15-bit programmable gain and 12-bit plus sign programmable offset adjustment for each channel. The improved internal track-and-hold amplifier and the extended self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing 9.1/9.0 Effective Number of Bits (ENOB) with a 100 MHz input signal and a 1.0/1.5 GHz sample rate while providing a 10-18 Code Error Rate (CER) Dissipating a typical 2.77/3.59 Watts in Non-Demultiplex Mode at 1.0/1.5 GSPS from a single 1.9V supply, this device is specified to have no missing codes over the full operating temperature range.

Each channel has its own independent DDR Data Clock, DCLKI and DCLKQ, which are in phase when both channels are powered up, so that only one Data Clock could be used to capture all data, which is sent out at the same rate as the input sample clock. If the 1:2 Demux Mode is selected, a second 10-bit LVDS bus becomes active for each channel, such that the output data rate is sent out two times slower to relax data-capture timing requirements. The part can also be used as a single 2.0/3.0 GSPS ADC to sample one of the I or Q inputs. The output formatting can be programmed to be offset binary or two's complement and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V to allow for power reduction for well-controlled back planes.

The ADC10D1000/1500 is the latest advance in TI's Ultra-High-Speed ADC family. This low-power, high-performance CMOS analog-to-digital converter digitizes signals at 10-bit resolution for dual channels at sampling rates of up to 1.0/1.5 GSPS (Non-DES Mode) or for a single channel up to 2.0/3.0 GSPS (DES Mode). The ADC10D1000/1500 achieves excellent accuracy and dynamic performance while dissipating less than 2.8/3.6 Watts. The product is packaged in a leaded or lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40°C to +85°C.

The ADC10D1000/1500 builds upon the features, architecture and functionality of the 8-bit GHz family of ADCs. An expanded feature set includes AutoSync for multi-chip synchronization, 15-bit programmable gain and 12-bit plus sign programmable offset adjustment for each channel. The improved internal track-and-hold amplifier and the extended self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing 9.1/9.0 Effective Number of Bits (ENOB) with a 100 MHz input signal and a 1.0/1.5 GHz sample rate while providing a 10-18 Code Error Rate (CER) Dissipating a typical 2.77/3.59 Watts in Non-Demultiplex Mode at 1.0/1.5 GSPS from a single 1.9V supply, this device is specified to have no missing codes over the full operating temperature range.

Each channel has its own independent DDR Data Clock, DCLKI and DCLKQ, which are in phase when both channels are powered up, so that only one Data Clock could be used to capture all data, which is sent out at the same rate as the input sample clock. If the 1:2 Demux Mode is selected, a second 10-bit LVDS bus becomes active for each channel, such that the output data rate is sent out two times slower to relax data-capture timing requirements. The part can also be used as a single 2.0/3.0 GSPS ADC to sample one of the I or Q inputs. The output formatting can be programmed to be offset binary or two's complement and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V to allow for power reduction for well-controlled back planes.

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类型 标题 下载最新的英语版本 日期
* 数据表 ADC10D1000/1500 Low Power, 10-Bit, Dual 1.0/1.5 GSPS or Single 2.0/3.0 GSPS ADC 数据表 (Rev. Q) 2013年 3月 15日
应用手册 AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (Rev. G) 2017年 2月 3日
应用手册 Maximizing SFDR Performance in the GSPS ADC: Spur Sources and Methods of Mitigat 2013年 12月 9日
应用手册 AN-2128 ADC1xD1x00 Pin Compatibility (Rev. C) 2013年 5月 1日
用户指南 Schematic and Layout Recommendations for the GSPS ADC 2013年 4月 29日
应用手册 AN-2177 Using the LMH6554 as a ADC Driver (Rev. A) 2013年 4月 26日
应用手册 From Sample Instant to Data Output: Understanding Latency in the GSPS ADC 2012年 12月 18日

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评估板

ADC-LD-BB — ADC 低失真不平衡变压器板

One ADC-LD-BB board is included in the hardware kit with the GSPS analog-to-digital converter (ADC) reference boards. Since the analog inputs to the ADC1xDxx00RB are differential and most signal sources are single ended, these balun boards are generally used to achieve (...)

用户指南: PDF
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支持软件

WAVEVISION5 WaveVision 5 Software

WaveVision 5 software is part of the WaveVision evaluation system that also includes WaveVision 5 Data Capture Board. The WaveVision 5 system is an easy-to-use data acquisition and analysis tool, designed to help users evaluate Texas Instruments' Signal Path solutions.

While WaveVision 5 software (...)

支持的产品和硬件

支持的产品和硬件

产品
高速 ADC (≥10MSPS)
ADC08D1020 8 位、双路 1.0GSPS 或单路 2.0GSPS 模数转换器 (ADC) ADC08D1520 8 位、双路 1.5GSPS 或单路 3.0GSPS 模数转换器 (ADC) ADC10D1000 10 位、双通道 1.0GSPS 或单路 2.0GSPS 模数转换器 (ADC) ADC10D1500 10 位、双通道 1.5GSPS 或单通道 3.0GSPS 模数转换器 (ADC) ADC10DV200 双通道、10 位、200MSPS 模数转换器 (ADC) ADC12D1000 12 位、双通道 1.0GSPS 或单通道 2.0GSPS 模数转换器 (ADC) ADC12D1000RF 12 位、双通道 1.0GSPS 或单通道 2.0GSPS 射频采样模数转换器 (ADC) ADC12D1600 12 位、双通道 1.6GSPS 或单通道 3.2GSPS 模数转换器 (ADC) ADC12D1600RF 12 位双通道 1.6GSPS 或单通道 3.2GSPS 射频采样模数转换器 (ADC) ADC12D1800 12 位、双通道 1.8GSPS 或单通道 3.6GSPS 模数转换器 (ADC) ADC12D1800RF 12 位、双通道 1.8GSPS 或单通道 3.6GSPS、射频采样模数转换器 (ADC) ADC12D500RF 12 位、双通道 500MSPS 或单通道 1.0GSPS 射频采样模数转换器 (ADC) ADC12D800RF 12 位、双通道 800MSPS 或单通道 1.6GSPS 射频采样模数转换器 (ADC) ADC14DC080 双通道、14 位、80MSPS、1.0GHz 输入带宽模数转换器 (ADC) ADC16DV160 双通道、16 位、160MSPS 模数转换器 (ADC) ADC16V130 16 位、130MSPS 模数转换器 (ADC)
硬件开发
评估板
ADC08D1520RB ADC08D1520RB:低功耗、8 位、双路 1.5 GSPS 或单路 3.0 GSPS 模数转换器参考板 ADC12D1600RB 12 位双路 1.6/1.8 GSPS 或单路 3.2/3.6 GSPS A/D 转换器参考板 ADC16DV160HFEB ADC16DV160HFEB 评估板 LM98640CVAL 具有 LVDS 输出的双通道、14 位、40 MSPS 模拟前端 WAVEVSN-BRD-5.1 WaveVision 5 数据捕获板(5.1 版)
软件
应用软件和框架
WAVEVISION5 Data Acquisition and Analysis Software
仿真模型

ADC10D1000 IBIS Model

SNAM011.ZIP (83 KB) - IBIS Model
模拟工具

PSPICE-FOR-TI — 适用于 TI 设计和模拟工具的 PSpice®

PSpice® for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence® 的模拟分析引擎。PSpice for TI 可免费使用,包括业内超大的模型库之一,涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助 PSpice for TI 的设计和仿真环境及其内置的模型库,您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案,然后再进行布局和制造,可缩短产品上市时间并降低开发成本。

在 PSpice for TI 设计和仿真工具中,您可以搜索 TI (...)
参考设计

TIDA-00113 — 在单通道模式或双通道模式下针对高带宽应用驱动 GSPS ADC

该设计旨在帮助系统设计人员权衡利弊,推动具有每秒千兆取样率的 ADC(采用平衡-非平衡变压器配置)在带宽应用中的应用,并对该实施过程进行优化。需考虑的权衡因素包括平衡-非平衡变压器的结构、插入损耗、动态性能、可配置性和实施的简便性。拓扑和布局在优化系统性能的过程中尤为重要,这也正是这些设计能够有助于缩短设计周期的原因所在。
设计指南: PDF
原理图: PDF
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  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
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  • 制造厂地点
  • 封装厂地点

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