产品详情

Sample rate (max) (Msps) 3000 Resolution (Bits) 8 Number of input channels 1 Interface type Parallel CMOS Analog input BW (MHz) 3000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.81 Power consumption (typ) (mW) 1600 Architecture Folding Interpolating SNR (dB) 45.3 ENOB (bit) 7.2 SFDR (dB) 55.4 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 3000 Resolution (Bits) 8 Number of input channels 1 Interface type Parallel CMOS Analog input BW (MHz) 3000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.81 Power consumption (typ) (mW) 1600 Architecture Folding Interpolating SNR (dB) 45.3 ENOB (bit) 7.2 SFDR (dB) 55.4 Operating temperature range (°C) -40 to 85 Input buffer Yes
HLQFP (NNB) 128 484 mm² 22 x 22
  • Single +1.9V ±0.1V Operation
  • Choice of SDR or DDR Output Clocking
  • Internal selectable 4K Data Buffer
  • Serial Interface for Extended Control
  • Adjustment of Input Full-Scale Range, Offset and Clock Phase
  • Duty Cycle Corrected Sample Clock
  • Test Pattern Output Capability

Key Specifications

  • Resolution: 8 Bits
  • Max Conversion Rate: 3 Gsps (min)
  • Code Error Rate: 10-18 (typ)
  • ENOB @ 748 MHz Input: 7.1 Bits (typ)
  • SNR @ 748 MHz: 44.9 dB (typ)
  • Full Power Bandwidth: 3 GHz (typ)
  • Power Consumption
    • Full Power Capure: 1.6 W (typ)
    • Power Down Mode: 25 mW (typ)

All trademarks are the property of their respective owners.

  • Single +1.9V ±0.1V Operation
  • Choice of SDR or DDR Output Clocking
  • Internal selectable 4K Data Buffer
  • Serial Interface for Extended Control
  • Adjustment of Input Full-Scale Range, Offset and Clock Phase
  • Duty Cycle Corrected Sample Clock
  • Test Pattern Output Capability

Key Specifications

  • Resolution: 8 Bits
  • Max Conversion Rate: 3 Gsps (min)
  • Code Error Rate: 10-18 (typ)
  • ENOB @ 748 MHz Input: 7.1 Bits (typ)
  • SNR @ 748 MHz: 44.9 dB (typ)
  • Full Power Bandwidth: 3 GHz (typ)
  • Power Consumption
    • Full Power Capure: 1.6 W (typ)
    • Power Down Mode: 25 mW (typ)

All trademarks are the property of their respective owners.

The ADC08B3000 is a single, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sample rates up to 3.4 Gigasamples Per Second, (Gsps). Consuming a typical 1.6 Watts at 3 Gsps from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the calibration scheme enable an excellent response of all dynamic parameters up to Nyquist, producing a high 7.1 Effective Number Of Bits, (ENOB), with a 748 MHz input signal and a 3 GHz sample rate while providing a 10-18 Code Error Rate. A sample rate of 3 Gsps is achieved by interleaving two ADCs, each operating at 1.5 Gsps. Output formatting is offset binary. The device contains a 4K Capture Buffer with output on two 8-bit Low Voltage CMOS (LVCMOS) output buses at rates up to 200MHz.

The converter typically consumes less than 25 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad HLQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range.

The ADC08B3000 is a single, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sample rates up to 3.4 Gigasamples Per Second, (Gsps). Consuming a typical 1.6 Watts at 3 Gsps from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the calibration scheme enable an excellent response of all dynamic parameters up to Nyquist, producing a high 7.1 Effective Number Of Bits, (ENOB), with a 748 MHz input signal and a 3 GHz sample rate while providing a 10-18 Code Error Rate. A sample rate of 3 Gsps is achieved by interleaving two ADCs, each operating at 1.5 Gsps. Output formatting is offset binary. The device contains a 4K Capture Buffer with output on two 8-bit Low Voltage CMOS (LVCMOS) output buses at rates up to 200MHz.

The converter typically consumes less than 25 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad HLQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range.

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类型 标题 下载最新的英语版本 日期
* 数据表 ADC08B3000 8-Bit, 3 GSPS, High Perf Low Pwr ADC w/4K Buffer 数据表 (Rev. M) 2013年 4月 18日
用户指南 Single low power, ultra high speed CMOS A D Converter with data buffer 2012年 1月 25日

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  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
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