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描述

The PMP30164 reference design uses the UCC28740 constant current (CC), constant voltage (CV) Valley Switching Flyback controller to generate two outputs (5V, 12V). The maximum peak output power is 28W (<20s). The design is optimized for a nominal output power of 1W and is capable of delivering (...)

主要特色

  • 3 phase input
  • Wide AC input range (140VAC - 474VAC)
  • Low standby power
  • Excellent transient performance
  • Test report available

Design Parameters

 
 
Vin (V) (Min)
Vin (V) (Min)
Vin (V) (Max)
Vin (V) (Max)
Vout (V) (Nom)
Vout (V) (Nom)
Iout (A) (Max)
Iout (A) (Max)
Output Power (W)
Output Power (W)
隔离/非隔离
隔离/非隔离
输入类型
输入类型
拓扑
拓扑
Designed for
Designed for
PMP30164.1
(Output Voltage 1)
140 274 12 1.5 18 Isolated AC Flyback
PMP30164.2
(Output Voltage 2)
140 274 5 2 10 Isolated AC Flyback

描述

The TPS543C20 is a highly integrated, synchronous buck converter tailored for high density power solutions wich features high performance integrated MOSFETs with very low RDSon to achieve high efficiency. This converter enables the design of a 1V, 20A power supply capable of acheiving efficiency (...)

主要特色

  • Integrated power stage using NexFET technology with very low RDSon, >88% efficiency at 20A load current
  • Selectable voltage reference and programmable switchinig frequency allowing for great design flexibility
  • Differentially enhanced control loop requiring no external compensation
  • Temperature rise < 17o (...)

Design Parameters

 
 
Vin (V) (Min)
Vin (V) (Min)
Vin (V) (Max)
Vin (V) (Max)
Vout (V) (Nom)
Vout (V) (Nom)
Iout (A) (Max)
Iout (A) (Max)
Output Power (W)
Output Power (W)
隔离/非隔离
隔离/非隔离
输入类型
输入类型
拓扑
拓扑
Designed for
Designed for
PMP20050.1
(Output
Voltage1)
4.5 15 1 20 20 Non-Isolated DC Buck- Synchronous

描述

The TIDA-01053 is an ADC driver reference design to optimize the THD, noise and the full system SNR for the high dynamic range instrumentation. The high capacitive nature of the ADC input presents some unique challenges for driver design and part selection process to ensure stability, low noise (...)

主要特色

  • ADC driver design for best noise and THD performance
  • Fully differential driver
  • Dual op amp configuration
  • Noise and THD measurements for the standalone driver

描述

The TIDA-00299 reference design implements a cost-optimized EtherCAT® slave (dual ports) with SPI interface to the application processor. The hardware design is capable of supporting multi-protocol industrial Ethernet and field busses using the AMIC110 industrial communications processor (...)

主要特色

  • Passes EtherCAT Slave Conformance Testing (CTT)
  • Software-programmable multi-protocol industrial ethernet and field bus support using AMIC110 communicatoin processor
  • SPI interface with flexibility to run EtherCAT slave stack with onboard AMIC110 processor or on application processor like C2000 MCU
  • (...)

描述

This reference design provides an efficient power supply scheme to power-up the RF-sampling DAC38RF8x digital-to-analog data converter (DAC) without sacrificing performance and also reduces board area and BOM. The reference design uses both DC/DC switchers and an LDO to power-up the DAC38RF8x while (...)

主要特色

  • Provides an Efficient Power Solution for RF-Sampling DACs
  • Enables Optimal Spur and Phase Noise Performance
  • Reduces Board Area
  • Lowers Bill of Materials (BOM) Cost

描述

Synthesis of waveforms appropriate for an S-band multifunction phased array radar (MPAR) is demonstrated with an RF sampling architecture utilizing the DAC38RF80, a 9GSPS 16-bit digital-to-analog converter (DAC). The RF sampling transmit architecture simplifies the signal chain, bringing the data (...)

主要特色

  • S-band transmitter reference design
  • Wideband frequency flexibility and planning
  • Demonstration using multichannel FM-modulated chirp waveforms
  • Tested reference design includes an evaluation module (EVM), configuration software, and User’s Guide

描述

The TIDA-00892 reference design provides a compact solution capable of generating isolated DC power while supporting isolated RS-485 communication. The design consists of a reinforced digital isolator with integrated power combined with an RS-485 communication transceiver.

主要特色

  • Small Combination Solution (Equal to ISOW7841 Device Footprint)
  • Single Power Supply Solution (No separate supply required for interface side)
  • Reduced BOM Cost
  • Extendable to Other Full-Duplex RS-485 Tranceivers

描述

The TIDA-01051 reference design is used to demonstrate optimized channel density, integration, power consumption, clock distribution and signal chain performance of very high channel count data acquisition (DAQ) systems such as those used in automatic test equipment (ATE). Using serializers, such as (...)

主要特色

  • Two 20 bit SAR ADC channels (expendable up to 28)
  • Three level MUX tree (up to 64 channels per ADC)
  • Highlights throughput improvements using serialized ADC output data
  • Modular front-end reference design for high channel count systems that can be repeated
  • Up to +/-12V input signal (+/-24Vpp differential)

描述

The objective of the TIDA-00994 reference design is to develop an embedded firmware of a multi-segment RGB signal tower used in factory floor and industrial process automation of greater complexity. A Wi-Fi ® interface is implemented to control the stack light and read back status information (...)

主要特色

  • Flexible and easy-to-control RGB LED tower light design
  • Different switchable modes: demo, temperature, humidity, and stack light
  • Controllable through wi-fi interface
  • One to five RGB LED segments with four individual channels each
  • Adjustable maximum LED current up to 60 mA per channel

描述

This reference design consists of an analog front-end (AFE) signal chain for wideband receiver applications using the LMH2832 digitally controlled variable gain amplifier (DVGA) and ADS54J40 analog-to-digital converter (ADC). The design is primarily targeted for upstream DOCSIS 3.1 receiver (...)

主要特色

  • AC-coupled signal path from 100 kHz to 204 MHz with 196 MHz of upstream-signal-bandwidth support for DOCSIS 3.1 applications
  • 58 dBFs of minimum system SNR (200 MHz BW) for –1-dBFs input at the ADC
  • 70 dBFs of minimum system SFDR for –1-dBFs input at the ADC
  • 1.71 A of average active-state current (...)

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