ZHCSJC1D
April 2019 – May 2021
CC3235S
,
CC3235SF
PRODUCTION DATA
1
特性
2
应用
3
说明
4
功能方框图
5
Revision History
6
Device Comparison
6.1
Related Products
7
Terminal Configuration and Functions
7.1
Pin Diagram
7.2
Pin Attributes
11
7.3
Signal Descriptions
13
7.4
Pin Multiplexing
7.5
Drive Strength and Reset States for Analog and Digital Multiplexed Pins
7.6
Pad State After Application of Power to Device, Before Reset Release
7.7
Connections for Unused Pins
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Power-On Hours (POH)
8.4
Recommended Operating Conditions
8.5
Current Consumption Summary (CC3235S)
24
25
8.6
Current Consumption Summary (CC3235SF)
27
28
8.7
TX Power Control for 2.4 GHz Band
8.8
TX Power Control for 5 GHz
8.9
Brownout and Blackout Conditions
8.10
Electrical Characteristics for GPIO Pins
33
34
8.11
Electrical Characteristics for Pin Internal Pullup and Pulldown
8.12
WLAN Receiver Characteristics
37
38
8.13
WLAN Transmitter Characteristics
40
41
8.14
WLAN Transmitter Out-of-Band Emissions
43
44
8.15
BLE/2.4 GHz Radio Coexistence and WLAN Coexistence Requirements
8.16
Thermal Resistance Characteristics for RGK Package
8.17
Timing and Switching Characteristics
8.17.1
Power Supply Sequencing
8.17.2
Device Reset
8.17.3
Reset Timing
8.17.3.1
nRESET (32-kHz Crystal)
52
53
8.17.3.2
nRESET (External 32-kHz Clock)
55
8.17.4
Wakeup From HIBERNATE Mode
8.17.5
Clock Specifications
8.17.5.1
Slow Clock Using Internal Oscillator
8.17.5.2
Slow Clock Using an External Clock
60
8.17.5.3
Fast Clock (Fref) Using an External Crystal
62
8.17.5.4
Fast Clock (Fref) Using an External Oscillator
64
8.17.6
Peripherals Timing
8.17.6.1
SPI
8.17.6.1.1
SPI Master
68
8.17.6.1.2
SPI Slave
70
8.17.6.2
I2S
8.17.6.2.1
I2S Transmit Mode
73
8.17.6.2.2
I2S Receive Mode
75
8.17.6.3
GPIOs
8.17.6.3.1
GPIO Output Transition Time Parameters (Vsupply = 3.3 V)
78
8.17.6.3.2
GPIO Input Transition Time Parameters
80
8.17.6.4
I2C
82
8.17.6.5
IEEE 1149.1 JTAG
84
8.17.6.6
ADC
86
8.17.6.7
Camera Parallel Port
88
8.17.6.8
UART
8.17.6.9
SD Host
8.17.6.10
Timers
9
Detailed Description
9.1
Overview
9.2
Arm® Cortex®-M4 Processor Core Subsystem
9.3
Wi-Fi® Network Processor Subsystem
9.3.1
WLAN
9.3.2
Network Stack
9.4
Security
9.5
FIPS 140-2 Level 1 Certification
9.6
Power-Management Subsystem
9.7
Low-Power Operating Mode
9.8
Memory
9.8.1
External Memory Requirements
9.8.2
Internal Memory
9.8.2.1
SRAM
9.8.2.2
ROM
9.8.2.3
Flash Memory
9.8.2.4
Memory Map
9.9
Restoring Factory Default Configuration
9.10
Boot Modes
9.10.1
Boot Mode List
9.11
Hostless Mode
10
Applications, Implementation, and Layout
10.1
Application Information
10.1.1
BLE/2.4 GHz Radio Coexistence
10.1.2
Antenna Selection
10.1.3
Typical Application
10.2
PCB Layout Guidelines
10.2.1
General PCB Guidelines
10.2.2
Power Layout and Routing
10.2.2.1
Design Considerations
10.2.3
Clock Interface Guidelines
10.2.4
Digital Input and Output Guidelines
10.2.5
RF Interface Guidelines
11
Device and Documentation Support
11.1
第三方产品免责声明
11.2
Tools and Software
11.3
Firmware Updates
11.4
Device Nomenclature
11.5
Documentation Support
11.6
Related Links
11.7
支持资源
11.8
Trademarks
11.9
静电放电警告
11.10
Export Control Notice
11.11
术语表
12
Mechanical, Packaging, and Orderable Information
12.1
Packaging Information
12.1.1
Package Option Addendum
12.1.1.1
Packaging Information
12.1.1.2
Tape and Reel Information