SNOSCY4E March 2015 – October 2018
PRODUCTION DATA.
The LMG5200 has an UVLO on both the VCC and HB (bootstrap) supplies. When the VCC voltage is below the threshold voltage of 3.8 V, both the HI and LI inputs are ignored, to prevent the GaN FETs from being partially turned on. Also, if there is insufficient VCC voltage, the UVLO actively pulls the high- and low-side GaN FET gates low. When the HB to HS bootstrap voltage is below the UVLO threshold of 3.2 V, only the high-side GaN FET gate is pulled low. Both UVLO threshold voltages have 200 mV of hysteresis to avoid chattering.
CONDITION (VHB-HS > VHBR for all cases below) | HI | LI | SW |
---|---|---|---|
VCC - VSS < VCCR during device start-up | H | L | Hi-Z |
VCC - VSS < VCCR during device start-up | L | H | Hi-Z |
VCC - VSS < VCCR during device start-up | H | H | Hi-Z |
VCC - VSS < VCCR during device start-up | L | L | Hi-Z |
VCC - VSS < VCCR - VCC(hyst) after device start-up | H | L | Hi-Z |
VCC - VSS < VCCR - VCC(hyst) after device start-up | L | H | Hi-Z |
VCC - VSS < VCCR - VCC(hyst) after device start-up | H | H | Hi-Z |
VCC - VSS < VCCR - VCC(hyst) after device start-up | L | L | Hi-Z |
CONDITION (VCC > VCCR for all cases below) | HI | LI | SW |
---|---|---|---|
VHB-HS < VHBR during device start-up | H | L | Hi-Z |
VHB-HS < VHBR during device start-up | L | H | PGND |
VHB-HS < VHBR during device start-up | H | H | PGND |
VHB-HS < VHBR during device start-up | L | L | Hi-Z |
VHB-HS < VHBR - VHB(hyst) after device start-up | H | L | Hi-Z |
VHB-HS < VHBR - VHB(hyst) after device start-up | L | H | PGND |
VHB-HS < VHBR - VHB(hyst) after device start-up | H | H | PGND |
VHB-HS < VHBR - VHB(hyst) after device start-up | L | L | Hi-Z |