SLUSC99A July   2016  – January 2017 UCD3138128A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 PMBus/SMBus/I2C Timing
    8. 7.8 Typical Characteristics
    9. 7.9 Timing Diagrams
  8. 8 Parametric Measurement Information
    1. 8.1 Typical Clock Gating Power Savings
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 ARM Processor
      2. 9.1.2 Memory
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  System Module
        1. 9.3.1.1 Address Decoder (DEC)
        2. 9.3.1.2 Memory Management Controller (MMC)
        3. 9.3.1.3 System Management (SYS)
        4. 9.3.1.4 Central Interrupt Module (CIM)
      2. 9.3.2  Peripherals
        1. 9.3.2.1 Digital Power Peripherals (DPPs)
          1. 9.3.2.1.1 Front End
          2. 9.3.2.1.2 DPWM Module
          3. 9.3.2.1.3 DPWM Events
          4. 9.3.2.1.4 High Resolution DPWM
          5. 9.3.2.1.5 Oversampling
          6. 9.3.2.1.6 DPWM Interrupt Generation
          7. 9.3.2.1.7 DPWM Interrupt Scaling/Range
          8. 9.3.2.1.8 Synchronous Rectifier Dead Time Optimization Peripheral
      3. 9.3.3  Automatic Mode Switching
        1. 9.3.3.1 Phase Shifted Full Bridge Example
        2. 9.3.3.2 LLC Example
        3. 9.3.3.3 Mechanism For Automatic Mode Switching
      4. 9.3.4  DPWMC, Edge Generation, Intramux
      5. 9.3.5  Synchronous Rectifier MOSFET Ramp And IDE Calculation
      6. 9.3.6  Filter
        1. 9.3.6.1 Loop Multiplexer
        2. 9.3.6.2 Fault Multiplexer
      7. 9.3.7  Communication Ports
        1. 9.3.7.1 SCI (UART) Serial Communication Interface
        2. 9.3.7.2 PMBUS/I2C
          1. 9.3.7.2.1 Example: PMBus Address Decode via ADC12 Reading
        3. 9.3.7.3 SPI
        4. 9.3.7.4 JTAG Standard Interface
      8. 9.3.8  Real Time Clock
      9. 9.3.9  External Crystal Interface
      10. 9.3.10 Timers
        1. 9.3.10.1 24-Bit Timer
        2. 9.3.10.2 16-Bit PWM Timers
        3. 9.3.10.3 Watchdog Timer
      11. 9.3.11 General Purpose ADC12
      12. 9.3.12 Miscellaneous Analog
      13. 9.3.13 Brownout
      14. 9.3.14 Global I/O
      15. 9.3.15 Temperature Sensor Control
      16. 9.3.16 I/O Mux Control
      17. 9.3.17 Current Sharing Control
      18. 9.3.18 Temperature Reference
    4. 9.4 Device Functional Modes
      1. 9.4.1 DPWM Modes of Operation
        1. 9.4.1.1 Normal Mode
        2. 9.4.1.2 DPWM Multiple Output Mode
        3. 9.4.1.3 DPWM Resonant Mode
        4. 9.4.1.4 Triangular Mode
        5. 9.4.1.5 Leading Edge Mode
        6. 9.4.1.6 Phase Shifting
    5. 9.5 Register Maps
      1. 9.5.1 CPU Memory Map And Interrupts
        1. 9.5.1.1 Memory Map (After Reset Operation)
        2. 9.5.1.2 Memory Map (Normal Operation)
        3. 9.5.1.3 Memory Map (System And Peripherals Blocks)
      2. 9.5.2 Boot ROM
        1. 9.5.2.1 Pseudo Code for ROM
      3. 9.5.3 Customer Boot Program
      4. 9.5.4 Flash Management
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 PCMC (Peak Current Mode Control) PSFB (Phase Shifted Full Bridge) Hardware Configuration Overview
        2. 10.2.2.2 DPWM Initialization for PSFB
        3. 10.2.2.3 DPWM Synchronization
        4. 10.2.2.4 Fixed Signals to Bridge
        5. 10.2.2.5 Dynamic Signals to Bridge
      3. 10.2.3 System Initialization for PCM
        1. 10.2.3.1 Use of Front Ends and Filters in PSFB
        2. 10.2.3.2 Peak Current Detection
        3. 10.2.3.3 Peak Current Mode (PCM)
      4. 10.2.4 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Device Grounding and Layout Guidelines
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
        1. 13.2.1.1 References
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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6 Pin Configuration and Functions

PFC Package
80 Pins (TQFP)
Top View
UCD3138128A po_slusc99.gif
Additional pin functionality is specified in the following table.

Pin Functions

PIN NAME PRIMARY ASSIGNMENT ALTERNATE ASSIGNMENT CONFIGURABLE
AS A GPIO?
NO. 1 NO. 2
1 AD13 12-bit ADC, Ch 13, comparator E, I-share DAC output
2 AD12 12-bit ADC, Ch 12
3 AD10 12-bit ADC, Ch 10
4 AD07 12-bit ADC, Ch 7, Connected to comparator F and reference to comparator G DAC output
5 AD06 12-bit ADC, Ch 6, Connected to comparator F DAC output
6 AD04 12-bit ADC, Ch 4, Connected to comparator D DAC output
7 AD03 12-bit ADC, Ch 3, Connected to comparator B and C
8 V33DIO Digital I/O 3.3V core supply
9 DGND Digital ground
10 RESET Device Reset Input, active low
11 PWM2 General purpose PWM 2 Yes
12 PWM3 General purpose PWM 3 Yes
13 TCAP1 Timer Capture Input TCAP0 Yes
14 ADC_EXT_TRIG ADC conversion external trigger input Yes
15 PMBUS_CLK PMBUS Clock (Open Drain) Yes
16 PMBUS_DATA PMBus data (Open Drain) Yes
17 PMBUS_ALERT PMBus Alert (Open Drain) Yes
18 PMBUS_CTRL PMBus Control (Open Drain) Yes
19 I2C_CLK I2C Clock Yes
20 I2C_DATA I2C Data Yes
21 DGND Digital ground
22 DPWM0A DPWM 0A output Yes
23 DPWM0B DPWM 0B output Yes
24 DPWM1A DPWM 1A output Yes
25 DPWM1B DPWM 1B output Yes
26 DPWM2A DPWM 2A output Yes
27 DPWM2B DPWM 2B output Yes
28 DPWM3A DPWM 3A output Yes
29 DPWM3B DPWM 3B output Yes
30 DTC0 Synchronous Rectifier dead time optimization control input 0 GPIOA Yes
31 DTC1 Synchronous Rectifier dead time optimization control input 1 GPIOB Yes
32 GPIOC General purpose IO C Yes
33 GPIOD General purpose IO D Yes
34 SYNC DPWM Synchronize pin Yes
35 SCI_TX0 SCI TX 0 Yes
36 SCI_RX0 SCI RX 0 Yes
37 SCI_TX1 SCI TX 1 Yes
38 SCI_RX1 SCI RX 1 Yes
39 PWM0 General purpose PWM 0 SYNC Yes
40 PWM1 General purpose PWM 1 Yes
41 DGND Digital ground
42 EXT_INT External Interrupt Yes
43 FAULT0 External fault input 0 Yes
44 FAULT1 External fault input 1 Yes
45 TCK(1) JTAG test clock. It is recommended that this pin is pulled LOW on the target. RTC_IN XTAL_CLK_OUT Yes
46 TDO(1) JTAG test data output. It is recommended that this pin is pulled HIGH on the target. TCAP0 TCAP1 Yes
47 TDI(1) JTAG test data input. It is recommended that this pin is pulled HIGH on the target. TCAP0 TCAP1 Yes
48 TMS(1) JTAG test mode select. This pin must be pulled HIGH on the target so that the effect of any spurious TCKs when there is no connection is benign. Yes
49 TCAP0 Timer Capture Input TCAP1 Yes
50 SPI_CS SPI Chip Select Yes
51 SPI_CLK SPI Clock Yes
52 SPI_MOSI SPI Master Output Slave Input Yes
53 SPI_MISO SPI Master Input Slave Output Yes
54 FAULT2 External fault input 2 Yes
55 FAULT3 External fault input 3 Yes
56 DGND Digital ground
57 V33DIO Digital I/O 3.3-V core supply
58 BP18 1.8V Bypass (For internal use only, do not load)
59 V33D Digital 3.3-V core supply
60 DGND Digital ground
61 XTAL_OUT Crystal oscillator input
62 XTAL_IN Crystal oscillator output
63 AGND Analog ground
64 EAP0 Channel #0, differential analog voltage, positive input
65 EAN0 Channel #0, differential analog voltage, negative input
66 EAP1 Channel #1, differential analog voltage, positive input
67 EAN1 Channel #1, differential analog voltage, negative input
68 EAP2 Channel #2, differential analog voltage, positive input
69 EAN2 Channel #2, differential analog voltage, negative input
70 AGND Analog ground
71 V33A Analog 3.3V supply
72 AD00 12-bit ADC, Ch 0, Connected to current source
73 AD01 12-bit ADC, Ch 1, Connected to current source
74 AD02 12-bit ADC, Ch 2, Connected to comparator A, I-share
75 AD05 12-bit ADC, Ch 5
76 AD14 12-bit ADC, Ch 14
77 AD08 12-bit ADC, Ch 8
78 AD09 12-bit ADC, Ch 9
79 AD11 12-bit ADC, Ch 11
80 AGND Analog ground
(1) Fusion Digital Power based debug tools are recommended instead of JTAG.