ZHCSCX7B 数据表 | 德州仪器 TI.com.cn

ZHCSCX7B June 2014 – February 2017 UCD3138128 , UCD3138A64

PRODUCTION DATA.

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PFC|80
- MTQF009B

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8 Specifications

8.1 Absolute Maximum Ratings ⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

		VALUE		UNIT
		MIN	MAX
V33D	V33D to DGND	–0.3	3.8	V
V33DIO	V33DIO to DGND	–0.3	3.8	V
V33A	V33A to AGND	–0.3	3.8	V
BP18	BP18 to DGND	-0.3	2.5	V
\|DGND – AGND\|	Ground difference		0.3	V
RTC_IN_1_8/RSVD		-0.3	3.0	V
All Pins, excluding AGND⁽²⁾	Voltage applied to any pin	–0.3	3.8	V
T_OPT	Junction Temperature	–40	125	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Referenced to DGND

8.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range		–55	150	°C
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	–2000	2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	–500	500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

		MIN	TYP	MAX	UNIT
V33D	Digital power	3.0	3.3	3.6	V
V33DIO	Digital I/O power	3.0	3.3	3.6	V
V33A	Analog power	3.0	3.3	3.6	V
BP18	1.8 V digital power	1.6	1.8	2.0	V
T_J	Junction temperature	-40	-	125	°C

8.4 Thermal Information

THERMAL METRIC⁽¹⁾		80-PIN QFN	UNIT
R_θJA	Junction-to-ambient thermal resistance	47.8	°C/W
R_θJCtop	Junction-to-case (top) thermal resistance	7.8
R_θJB	Junction-to-board thermal resistance	24.4
ψ_JT	Junction-to-top characterization parameter	0.2
ψ_JB	Junction-to-board characterization parameter	24.0
R_θJCbot	Junction-to-case (bottom) thermal resistance	N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

V33A = V33D = V33DIO = 3.3V; 1μF from BP18 to DGND, T_J = –40°C to 125°C (unless otherwise noted)

PARAMETER		TEST CONDITION	MIN	TYP	MAX	UNIT
SUPPLY CURRENT
	I33A⁽⁵⁾	Measured on V33A. The device is powered up but all ADC12 and EADC sampling is disabled		6.3		mA
	I33DIO⁽⁵⁾	All GPIO and communication pins are open		0.35		mA
	I33D⁽⁵⁾	ROM program execution		69		mA
	I33	The device is in ROM mode with all DPWMs enabled and switching at 2 MHz. The DPWMs are all unloaded.		93	100	mA
ERROR ADC INPUTS EAP, EAN
	EAP – AGND		–0.15		1.998	V
	EAP – EAN		–0.256		1.848	V
	Typical error range	AFE = 0	–256		248	mV
	EAP – EAN Error voltage digital resolution	AFE = 3	0.8	1	1.20	mV
		AFE = 2	1.7	2	2.30	mV
		AFE = 1	3.55	4	4.45	mV
		AFE = 0	6.90	8	9.10	mV
R_EA	Input impedance (See Figure 9)	AGND reference	0.5			MΩ
I_OFFSET	Input offset current (See Figure 9)		–5		5	μA
	EADC Offset	Input voltage = 0 V at AFE = 0	–16		16	mV
		Input voltage = 0 V at AFE = 1	–10		10	mV
		Input voltage = 0 V at AFE = 2	–6		-6	mV
		Input voltage = 0 V at AFE = 3	–4		4	mV
	Sample Rate				15.625	MHz
	Analog Front End Amplifier Bandwidth			100		MHz
A₀	Gain	See Figure 10		1		V/V
A₀	Minimum output voltage				21	mV
EADC DAC
	DAC range		0		1.6	V
	VREF DAC reference resolution	10 bit, No dithering enabled		1.56		mV
	VREF DAC reference resolution	With 4 bit dithering enabled		97.6		μV
	INL		–1.5		1.5	LSB
	DNL		–1.0		2.1	LSB
	DAC reference voltage		1.58		1.61	V
ADC12
I_BIAS	Bias current for PMBus address pins		9.5		10.5	μA
	Measurement range for voltage monitoring		0		2.5	V
	Internal ADC reference voltage	–40°C to 125°C	2.475	2.500	2.53	V
	Change in Internal ADC reference from 25°C reference voltage⁽⁵⁾	–40°C to 25°C		–0.7		mV
		25°C to 125°C	-6			mV
	ADC12 INL integral nonlinearity⁽⁵⁾	ADC_SAMPLING_SEL = 6 for all ADC12 data, 25 °C to 125 °C		-7.5/+2.9		LSB
	ADC12 DNL differential nonlinearity⁽⁵⁾			–0.7/+3.2		LSB
	ADC Zero Scale Error		–7	±5	7	mV
	ADC Full Scale Error		–35	±20	35	mV
	Input bias	2.5 V applied to pin			200	nA
	Input leakage resistance⁽⁵⁾	ADC_SAMPLING_SEL= 6 or 0		1		MΩ
	Input Capacitance⁽⁵⁾			10		pF
DIGITAL INPUTS/OUTPUTS⁽¹⁾⁽²⁾
V_OL	Low-level output voltage⁽³⁾	I_OH = 4 mA, V33DIO = 3 V			DGND + 0.25	V
V_OH	High-level output voltage ⁽³⁾	I_OH = –4 mA, V33DIO = 3 V	V33DIO – 0.6			V
V_IH	High-level input voltage	V33DIO = 3 V	2.1			V
V_IL	Low-level input voltage	V33DIO = 3 V			1.1	V
I_OH	Output sinking current				4	mA
I_OL	Output sourcing current		–4			mA
SYSTEM PERFORMANCE
	Processor master clock (MCLK)			31.25		MHz
t_Delay	Digital filter delay⁽⁴⁾	(1 clock = 32ns)			6	MCLKs
f_(PCLK)	Internal oscillator frequency		240	250	260	MHz
I_SHARE	Current share current source (See Figure 28)		238		259	μA
R_SHARE	Current share resistor (See Figure 28)		9.7		10.3	kΩ
POWER ON RESET AND BROWN OUT (V33A pin, See Figure 3)
VGH		Voltage good High		2.7		V
VGL		Voltage good Low		2.5		V
V_res	Voltage at which IReset signal is valid⁽⁵⁾			0.8		V
	Brownout	Internal signal warning of brownout conditions		2.9		V
TEMPERATURE SENSOR⁽⁵⁾
V_TEMP		Voltage range of sensor	1.46		2.44	V
	Voltage resolution	Volts/°C		6.3		mV/ºC
	Temperature resolution	Degree C per bit		0.0969		ºC/LSB
	Accuracy⁽⁵⁾⁽⁶⁾	-40°C to 125°C	–10	±5	10	ºC
	Temperature range	-40°C to 125°C	–40		125	ºC
I_TEMP		Current draw of sensor when active		30		μA
V_AMB	Ambient temperature	Trimmed 25°C reading		1.87		V
ANALOG COMPARATOR
DAC	Reference DAC Range		0		2.5	V
	Reference Voltage		2.478	2.5	2.513	V
	Bits			7		bits
	INL⁽⁵⁾		–0.42		0.21	LSB
	DNL⁽⁵⁾		0.06		0.12	LSB
	Offset		–5.5		19.5	mV
	Reference DAC buffered output load⁽⁷⁾		0.5		1	mA
	Buffer offset (-0.5 mA)				8.3	mV
	Buffer offset (1.0 mA)				17	mV
RTC INTERFACE
f_RTC	RTC external input frequency			10		MHz

(1) DPWM outputs are low after reset. Other GPIO pins are configured as inputs after reset.

(2) On the 40 pin package V33DIO is connected to V33D internally.

(3) The maximum total current, IOHmax and IOLmax for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified. Maximum sink current per pin = –6 mA at V_OL; maximum source current per pin = 6 mA at V_OH.

(4) Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay, which has no variation associated with it, must be accounted for when calculating the system dynamic response.

(5) Characterized by design and not production tested.

(6) Ambient temperature offset value from the TEMPSENCTRL register should be used to meet accuracy.

(7) Available from reference DACs for comparators D, E, F and G.

8.6 Timing Characteristics

V33A = V33D = V33DIO = 3.3V; 1μF from BP18 to DGND, T_J = –40°C to 125°C (unless otherwise noted)

PARAMETER		TEST CONDITION	MIN	TYP	MAX	UNIT
EADC DAC
t	Settling Time	From 10% to 90%		250		ns
ADC12
	ADC single sample conversion time⁽²⁾	ADC_SAMPLING_SEL= 6 or 0		3.9		μs
SYSTEM PERFORMANCE
TWD	Watchdog time out resolution	Total time is: TWD x (WDCTRL.PERIOD+1)	10.5	13.3	17	ms
	Time to disable DPWM output based on active FAULT pin signal	High level on FAULT pin		66		ns
	Flash Read			1		MCLKs
t_Delay	Digital filter delay⁽¹⁾	(1 clock = 32ns)			6	MCLKs
	Retention period of flash content (data retention and program)	T_J= 25°C	100			years
	Program time to erase one page or block in data flash or program flash			20		ms
	Program time to write one word in program flash			50		µs
	Program time to write one word in data flash			40		µs
	Sync-in/sync-out pulse width	Sync pin		256		ns
POWER ON RESET AND BROWN OUT (V33A pin, See Figure 3)
t_POR		Time delay after Power is good or RESET* relinquished		1		ms
t_EXC1	The time it takes from the device to exit a reset state and begin executing the boot flash.⁽²⁾	I_RESET goes from a low state to a high state. This is approximately equivalent to toggling the external reset pin from low to high state.		0.5		ms
t_EXC2	The time it takes from the device to exit a reset state and begin executing program flash bank 0 (32 kB).⁽²⁾	I_RESET goes from a low state to a high state. This is approximately equivalent to toggling the external reset pin from low to high state.		3		ms
t_EXCT	The time it takes from the device to exit a reset state and begin executing the total program flash (64 kB).⁽²⁾	I_RESET goes from a low state to a high state. This is approximately equivalent to toggling the external reset pin from low to high state.		6		ms
TEMPERATURE SENSOR⁽²⁾
t_ON		Turn on time / settling time of sensor		100		μs
ANALOG COMPARATOR
	Bits			7		bits
	INL⁽²⁾		–0.42		0.21	LSB
	DNL⁽²⁾		0.06		0.12	LSB
	Time to disable DPWM output based on 0 V to 2.5 V step input on the analog comparator.⁽²⁾			90	150	ns

(1) Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay, which has no variation associated with it, must be accounted for when calculating the system dynamic response.

(2) Characterized by design and not production tested.

8.7 PMBUS/SMBUS/IC Timing²

The timing characteristics and timing diagram for the communications interface that supports I²C, SMBus, and PMBus in Slave or Master mode are shown in the Timing Requirements, Figure 1, and Figure 2. The numbers in the Timing Requirements are for 400 kHz operating frequency. However, the device supports two speeds, standard (100 kHz) and fast (400 kHz).

8.8 Timing Requirements

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
Typical values at T_A = 25°C and VCC = 3.3 V (unless otherwise noted)
f_SMB	SMBus/PMBus operating frequency	Slave mode, SMBC 50% duty cycle		100	400	kHz
f_I2C	I²C operating frequency	Slave mode, SCL 50% duty cycle		100	400	kHz
t_(BUF)	Bus free time between start and stop⁽⁵⁾			1.3		µs
t_(HD:STA)	Hold time after (repeated) start⁽⁵⁾			0.6		µs
t_(SU:STA)	Repeated start setup time⁽⁵⁾			0.6		µs
t_(SU:STO)	Stop setup time⁽⁵⁾			0.6		µs
t_(HD:DAT)	Data hold time	Receive mode		0		ns
t_(SU:DAT)	Data setup time			100		ns
t_(TIMEOUT)	Error signal/detect⁽¹⁾				35	ms
t_(LOW)	Clock low period		1.3			µs
t_(HIGH)	Clock high period⁽²⁾				35	ms
t_(LOW:SEXT)	Cumulative clock low slave extend time⁽³⁾				25	ms
t_f	Clock/data fall time	Rise time t_r = (V_ILmax – 0.15) to (V_IHmin + 0.15)	20 + 0.1 Cb⁽⁴⁾		300	ns
t_r	Clock/data rise time	Fall time t_f = 0.9 VDD to (V_ILmax – 0.15)	20 + 0.1 Cb⁽⁴⁾		300	ns
C_b	Total capacitance of one bus line				400	pF

(1) The device times out when any clock low exceeds t_(TIMEOUT).

(2) t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0).

(3) t_(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.

(4) C_b (pF)

(5) Fast mode, 400 kHz

UCD3138128 UCD3138A64 I2C_tim_dia_lusap2.gif

Figure 1. IC/SMBUS/PMBUS Timing Diagram²

UCD3138128 UCD3138A64 bus_timing_lusap2.gif

Figure 2. Bus Timing In Extended Mode

8.9 Power On Reset (POR) / Brown Out Detect (BOD)

UCD3138128 UCD3138A64 POR_BOR_slusbz8.gif

Figure 3. Power On Reset (POR) / Brown Out Reset (BOR)

VGH –	This is the V33A threshold where the internal power is declared good. The UCD3138x comes out of reset when above this threshold.
VGL –	This is the V33A threshold where the internal power is declared bad. The device goes into reset when below this threshold.
V_res –	This is the V33A threshold where the internal reset signal is no longer valid. Below this threshold the device is in an indeterminate state.
I_Reset –	This is the internal reset signal. When low, the device is held in reset. This is equivalent to holding the reset pin on the IC low.
t_POR –	The time delay from when VGH is exceeded to when the device comes out of reset.
Brown Out –	This is the V33A voltage threshold at which the device sets the brown out status bit. In addition an interrupt can be triggered if enabled.

8.10 Typical Clock Gating Power Savings

UCD3138128 UCD3138A64 UCD3138064_clock_gating_pwer_savings3_SLUSB72.gif

The CLKGATECTRL register provides control bits that can enable or disable the clock to several peripherals such as, PCM, CPCC, digital filters, front ends, DPWMs, UARTs, ADC-12 and more.

By default, all these controls are enabled. If a specific peripheral is not used the clock gate can be disabled in order to block the propagation of the clock signal to that peripheral and therefore reduce the overall current consumption of the device. The power savings chart displays the power savings per module. For example there are 4 DPWM modules, therefore, if all 4 are disabled a total of ~20 mA can be saved.