ZHCSEK1B December   2013  – October 2015 UCC28722

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Bias Voltage Supply (VDD)
      2. 7.3.2 Ground (GND)
      3. 7.3.3 Voltage-Sense (VS)
      4. 7.3.4 Base Drive (DRV)
      5. 7.3.5 Current Sense (CS)
        1. 7.3.5.1 Example
      6. 7.3.6 Cable Compensation (CBC)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Primary-Side Voltage Regulation
      2. 7.4.2 Primary-Side Current Regulation
      3. 7.4.3 Valley Switching
      4. 7.4.4 Start-Up Operation
      5. 7.4.5 Fault Protection
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Stand-by Power Estimate
        2. 8.2.2.2 Input Bulk Capacitance and Minimum Bulk Voltage
        3. 8.2.2.3 Transformer Turns Ratio, Inductance, Primary-Peak Current
        4. 8.2.2.4 Transformer Parameter Verification
        5. 8.2.2.5 Output Capacitance
        6. 8.2.2.6 VDD Capacitance, CDD
        7. 8.2.2.7 VS Resistor Divider, Line Compensation, and Cable Compensation
        8. 8.2.2.8 Startup Resistance and Startup Time
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 器件命名规则
        1. 11.1.1.1 术语定义
          1. 11.1.1.1.1  法拉电容术语
          2. 11.1.1.1.2  占空比术语
          3. 11.1.1.1.3  频率术语(以赫兹为单位)
          4. 11.1.1.1.4  电流术语(以安培为单位)
          5. 11.1.1.1.5  电流和电压调节术语
          6. 11.1.1.1.6  变压器术语
          7. 11.1.1.1.7  功率术语(以瓦特为单位)
          8. 11.1.1.1.8  电阻术语(以 Ω 为单位)
          9. 11.1.1.1.9  时序术语(以秒为单位)
          10. 11.1.1.1.10 电压术语(以伏特为单位)
          11. 11.1.1.1.11 交流电压术语(以 VRMS 为单位)
          12. 11.1.1.1.12 效率术语
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The UCC28722 flyback power supply controller provides constant voltage (CV) and constant current (CC) output regulation to help meet USB-compliant adaptors and charger requirements. This device uses the information obtained from auxiliary winding sensing (VS) to control the output voltage and does not require optocoupler or TL431 feedback circuitry. Not requiring optocoupler feedback reduces the component count and makes the design more cost effective and efficient.

8.2 Typical Application

UCC28722 des_pro_lusbl7.gif Figure 19. Design Procedure Application Example

8.2.1 Design Requirements

The design parameters are listed in Table 1.

Table 1. Design Parameters

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
INPUT CHARACTERISTICS
VIN RMS Input Voltage 100 (VIN(MIN)) 115/230 240 V
fLINE Line Frequency 47 50/60 64 Hz
VIN(RUN) Brownout Voltage IOUT = Nom 70 V
OUTPUT CHARACTERISTICS
VOCV Output Voltage VIN = Nom, IOUT = NOM 4.75 5 5.25 V
VRIPPLE Output Voltage Ripple VIN = Nom, IO = Max 0.15 V
IOUT Output Current VIN = Min to Max 1 1.05 A
Output OVP IOUT = Min to Max 5.75 V
Transient Response
Load Step (ITRAN = 0.6 A) (0.1 to 0.6 A) or (0.6 to 0.1 A)
V= 0.9 V for Calculations
4.1 5 6 V
SYSTEMS CHARACTERISTICS
fMAX Switching Frequency 70 kHz
ƞ Full Load Efficiency (115/230 V RMS input) IOUT = 1 A 75%

8.2.2 Detailed Design Procedure

This procedure outlines the steps to design a constant-voltage, constant-current flyback converter using the UCC28722 controller. Refer to Figure 19 for component names and network locations. The design procedure equations use terms that are defined in Stand-by Power Estimate through Startup Resistance and Startup Time.

8.2.2.1 Stand-by Power Estimate

Assuming no-load stand-by power is a critical design parameter, determine estimated no-load power based on target converter maximum switching frequency and output power rating.

The followingEquation 7 estimates the stand-by power of the converter.

Equation 7. UCC28722 q_dp_Psb_conv_lusb41.gif

For a typical USB charger application, the bias power during no-load is approximately 2.5 mW. This is based on 25-V VDD and 100-µA bias current. The output preload resistor can be estimated by VOCV and the difference in the converter stand-by power and the bias power. Equation 8 shows output preload resistance accounts for bias power estimated at 2.5 mW.

Equation 8. UCC28722 q_dp_Rpl_lusb41.gif

Typical startup resistance values for RSTR range from 1 MΩ to 5MΩ to achieve 2 s startup time. The capacitor bulk voltage for the loss estimation is the highest voltage for the stand-by power measurement, typically 325 VDC, see Equation 9.

Equation 9. UCC28722 q_dp_Prstr_lusb41.gif

For the total stand-by power estimation add an estimated 2.5 mW for snubber loss to the converter stand-by power loss, see Equation 10 and Equation 11.

Equation 10. UCC28722 qu9_lusb86.gif
Equation 11. UCC28722 q_dp_Psb_lusb41.gif

8.2.2.2 Input Bulk Capacitance and Minimum Bulk Voltage

Determine the minimum voltage on the input capacitance, CB1 and CB2 total, in order to determine the maximum Np to Ns turns ratio of the transformer. The input power of the converter based on target full-load efficiency, minimum input RMS voltage, and minimum AC input frequency are used to determine the input capacitance requirement.

Maximum input power is determined based on VOCV, IOCC, and the full-load efficiency target, see Equation 12.

Equation 12. UCC28722 q_dp_Pin_lusb41.gif

Equation 13 provides an accurate solution for input capacitance based on a target minimum bulk capacitor voltage. To target a given input capacitance value, iterate the minimum capacitor voltage to achieve the target capacitance.

Equation 13. UCC28722 q_dp_Cbulk_lusb41.gif

8.2.2.3 Transformer Turns Ratio, Inductance, Primary-Peak Current

The maximum primary-to-secondary turns ratio can be determined by the target maximum switching frequency at full load, the minimum input capacitor bulk voltage, and the estimated DCM quasi-resonant time.

Initially determine the maximum available total duty cycle of the on time and secondary conduction time based on target switching frequency and DCM resonant time. For DCM resonant time, assume 500 kHz if you do not have an estimate from previous designs. For the transition mode operation limit, the period required from the end of secondary current conduction to the first valley of the VCE voltage is 1/2 of the DCM resonant period, or 1 µs assuming 500-kHz resonant frequency. DMAX can be determined using Equation 14.

Equation 14. UCC28722 q_dmax_lusb88.gif

Once DMAX is known, the maximum turns ratio of the primary to secondary can be determined with the equation below. DMAGCC is defined as the secondary diode conduction duty cycle during constant-current, CC, operation. It is set internally by the UCC28722 at 0.425. The total voltage on the secondary winding needs to be determined; which is the sum of VOCV, the secondary rectifier VF, and the cable compensation voltage (VOCBC). For the 5-V USB charger applications, a turns ratio range of 13 to 15 is typically used, see Equation 15.

Equation 15. UCC28722 q_dp_Npsmax_lusb41.gif

Once an optimum turns ratio is determined from a detailed transformer design, use this ratio for the following parameters.

The UCC28722 constant-current regulation is achieved by maintaining a maximum DMAG duty cycle of 0.425 at the maximum primary current setting. The transformer turns ratio and constant-current regulating voltage determine the current sense resistor for a target constant current.

Since not all of the energy stored in the transformer is transferred to the secondary, a transformer efficiency term is included in Equation 16. This efficiency number includes the core and winding losses, leakage inductance ratio, and bias power ratio to rated output power. For a 5-V, 1-A charger example, bias power of 1.5% is a good estimate. An overall transformer efficiency of 0.9 is a good estimate to include 3.5% leakage inductance, 5% core and winding loss, and 1.5% bias power.

Equation 16. UCC28722 qu14_lusb86.gif

The primary transformer inductance can be calculated using the standard energy storage equation for flyback transformers. Primary current, maximum switching frequency and output and transformer power losses are included in Equation 17 and Equation 18. Initially determine transformer primary current.

Primary current is simply the maximum current sense threshold divided by the current sense resistance.

Equation 17. UCC28722 q_dp_Ippmax_lusb41.gif
Equation 18. UCC28722 q_dp_Lp_lusb41.gif

The secondary winding to auxiliary winding transformer turns ratio (NAS) is determined by the lowest target operating output voltage in constant-current regulation and the VDD UVLO of the UCC28722. There is additional energy supplied to VDD from the transformer leakage inductance energy which allows a lower turns ratio to be used in many designs Equation 19

Equation 19. UCC28722 q_dp_Nas_lusb41.gif

8.2.2.4 Transformer Parameter Verification

The transformer turns ratio selected affects the transistor VC and secondary rectifier reverse voltage so these should be reviewed. The UCC28722 does require a minimum on time of the transistor (tON) and minimum DMAG time (tDMAG) of the secondary rectifier in the high line, minimum load condition. The selection of fMAX, LP and RCS affects the minimum tON and tDMAG.

The secondary rectifier and transistor voltage stress can be determined by Equation 20.

Equation 20. UCC28722 q_dp_Vrev_lusb41.gif

For the transistor VC voltage stress, Equation 21, an estimated leakage inductance voltage spike (VLK) needs to be included.

Equation 21. UCC28722 EQ_VCPK.gif

Equation 22 and Equation 23 are used to determine if the minimum tON target of 300 ns and minimum tDMAG target of 1.2 µs is achieved.

Equation 22. UCC28722 q_tonmin_lusb88.gif
Equation 23. UCC28722 q_tdmagmin_lusb88.gif

8.2.2.5 Output Capacitance

The output capacitance value is typically determined by the transient response requirement from no-load. For example, in some USB charger applications there is a requirement to maintain a minimum VO of 4.1 V with a load-step transient of 0 mA to 500 mA . Equation 24 assumes that the switching frequency can be at the UCC28722 minimum of fSW(min).

Equation 24. UCC28722 q_dp_Cout_lusb41.gif

Another consideration of the output capacitor is the ripple voltage requirement which is reviewed based on secondary peak current and ESR. A margin of 20% is added to the capacitor ESR requirement in Equation 25.

Equation 25. UCC28722 q_dp_Resr_lusb41.gif

8.2.2.6 VDD Capacitance, CDD

The capacitance on VDD needs to supply the device operating current until the output of the converter reaches the target minimum operating voltage in constant-current regulation. At this time, the auxiliary winding can sustain the voltage to the UCC28722. The total output current available to the load and to charge the output capacitors is the constant-current regulation target, IOCC. Equation 26 assumes all the output current of the flyback is available to charge the output capacitance from 0 V to VOCC. If the converter is going to be loaded during the time the output is ramping from 0 V to VOCC, that load current must be subtracted for the available output current limit value, IOCC. There is 1 V of margin added to VDD in the calculation.

Equation 26. UCC28722 qu24_lusbL7.gif

NOTE

The typical ceramic capacitor of sufficient ratings for use here varies considerably in effective capacitance as the voltage across the capacitor changes. As the capacitor voltage increases beyond 25% of its rated voltage, the effective capacitance can become significantly less than the nominal capacitance at zero bias. This equation calculated the effective capacitance needed over the 8V to 21V range, not the nominal zero bias capacitance required. Evaluation of the particular capacitor chosen for this function is strongly recommended to ensure adequate capacitance over the 8V to 21V range.

8.2.2.7 VS Resistor Divider, Line Compensation, and Cable Compensation

The VS divider resistors determine the output voltage regulation point of the flyback converter, also the high-side divider resistor (RS1) determines the line voltage at which the controller enables continuous DRV operation. RS1 is initially determined based on transformer auxiliary to primary turns ratio and desired input voltage operating threshold in Equation 27.

Equation 27. UCC28722 Eq01_RS1_slusbl7.gif

The low-side VS pin resistor is selected based on desired VO regulation voltage in Equation 28.

Equation 28. UCC28722 q_dp_Rs2_lusb41.gif

The UCC28722 can maintain tight constant-current regulation over input line by utilizing the line compensation feature. The line compensation resistor (RLC) value is determined by current flowing in RS1 and expected base drive and transistor turnoff delay in Equation 29. Assume a 50-ns internal delay in the UCC28722.

Equation 29. UCC28722 q_rlc_lusb88.gif

The UCC28722 has adjustable cable drop compensation. The resistance for the desired compensation level at the output terminals can be determined using Equation 30.

Equation 30. UCC28722 q_dp_Rcbc_lusb41.gif

8.2.2.8 Startup Resistance and Startup Time

When the VDD capacitor is known, there is a tradeoff to be made between startup time and overall standby input power to the converter. Faster startup time requires a smaller startup resistance, which results in higher standby input power in Equation 31.

Equation 31. UCC28722 q_dp_Rstr_lusb41.gif

8.2.3 Application Curves

UCC28722 C001_SLUSBL7.png Figure 20. Efficiency
UCC28722 Figure_23_slusbl7.png Figure 22. Output at Start-up 115-V RMS, 5-Ω Load
UCC28722 Figure_25_slusbl7.png
SPACE
Figure 24. Output at Start-up 230-V RMS, 5-Ω Load
UCC28722 Figure_27_slusbl7.png

NOTE:

CH1 = VOCV with 5-V offset, CH2 = IOUT
Figure 26. Load Transient (0.6- to 0.1-A Load Step)
UCC28722 Figure_22_slusbl7.png Figure 21. Output at Start-up 115-V RMS, No Load
UCC28722 Figure_24_slusbl7.png Figure 23. Output at Start-up 230-V RMS, No Load
UCC28722 Figure_26_slusbl7.png

NOTE:

CH1 = VOCV with 5-V offset, CH2 = IOUT
Figure 25. Load Transients (0.1- to 0.6-A Load Step)
UCC28722 Figure_28_sllusbl7.png Figure 27. Output Ripple CH1 = VOCV at Supply Output