10.1 Layout Guidelines

To increase the reliability and feasibility of the design it is recommended to adhere to the following guidelines for PCB layout. 

1. Minimize the high current loops to reduce parasitic capacitances and inductances.  At the same time, do not inadvertently make traces with a high dv/dt too wide as this will create a very good E-field antenna.
2. Separate the device signal ground from the high current power ground in order to isolate the noise away from the device substrate.  The separate grounds should, ideally, be tied together at the input capacitor on the primary side.
3. Return the sense resistor to the ground side of the input capacitor, instead of to the ground plane under the device.
4. The bypass capacitor on VDD must be placed as close as possible to the VDD and GND pins of the device.
5. The filter capacitor on CS must be placed as close as possible to the CS pin and GND pin of the device.
6. The filter capacitor on FB must be placed as close as possible to the FB and GND pins of the device.

10.2 Layout Example

The partial layout example shown in Figure 25 demonstrates an effective component and track arrangement for the printed circuit board. Actual board layout must conform to the constraints on a specific design, so many variations are possible.

Figure 25. Partial Layout Example Showing Component Placement