ZHCSJ20C August   2018  – March 2019 UCC21530-Q1

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     功能方框图
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety-Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Propagation Delay and Pulse Width Distortion
    2. 7.2 Rising and Falling Time
    3. 7.3 Input and Enable Response Time
    4. 7.4 Programable Dead Time
    5. 7.5 Power-Up UVLO Delay to OUTPUT
    6. 7.6 CMTI Testing
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in UCC21530-Q1
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable Pin
      2. 8.4.2 Programmable Dead Time (DT) Pin
        1. 8.4.2.1 DT Pin Tied to VCC
        2. 8.4.2.2 DT Pin Connected to a Programming Resistor between DT and GND Pins
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing INA/INB Input Filter
        2. 9.2.2.2 Select Dead Time Resistor and Capacitor
        3. 9.2.2.3 Gate Driver Output Resistor
        4. 9.2.2.4 Estimate Gate Driver Power Loss
        5. 9.2.2.5 Estimating Junction Temperature
        6. 9.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 9.2.2.6.1 Selecting a VCCI Capacitor
        7. 9.2.2.7 Other Application Example Circuits
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Component Placement Considerations
      2. 11.1.2 Grounding Considerations
      3. 11.1.3 High-Voltage Considerations
      4. 11.1.4 Thermal Considerations
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 相关链接
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 术语表
  13. 13机械、封装和可订购信息
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information
      2. 13.1.2 Tape and Reel Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Pin Configuration and Functions

DWK Package
14-Pin SOIC
Top View
UCC21530-Q1 pin16_SLUSDG3.gif

Pin Functions

PIN I/O(1) DESCRIPTION
NAME NO.
DT 6 I DT pin configuration:
  • Tying DT to VCCI disables the DT feature and allows the outputs to overlap.
  • Placing a resistor (RDT) between DT and GND adjusts dead time according to the equation: DT (in ns) = 10 × RDT (in kΩ). TI recommends bypassing this pin with a ceramic capacitor, 2.2 nF or greater, close to DT pin to achieve better noise immunity.
EN 5 I Enable both driver outputs if asserted high, disable the output if set low. It is recommended to tie this pin to VCCI if not used to achieve better noise immunity. Bypass using a ≈ 1-nF low ESR/ESL capacitor close to EN pin when connecting to a micro controller with distance.
GND 4 P Primary-side ground reference. All signals in the primary side are referenced to this ground.
INA 1 I Input signal for A channel. INA input has a TTL/CMOS compatible input threshold. This pin is pulled low internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise immunity.
INB 2 I Input signal for B channel. INB input has a TTL/CMOS compatible input threshold. This pin is pulled low internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise immunity.
NC 7 No internal connection.
OUTA 15 O Output of driver A. Connect to the gate of the A channel FET or IGBT.
OUTB 10 O Output of driver B. Connect to the gate of the B channel FET or IGBT.
VCCI 3 P Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor located as close to the device as possible.
VCCI 8 P Primary-side supply voltage. This pin is internally shorted to pin 3.
VDDA 16 P Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL capacitor located as close to the device as possible.
VDDB 11 P Secondary-side power for driver B. Locally decoupled to VSSB using low ESR/ESL capacitor located as close to the device as possible.
VSSA 14 P Ground for secondary-side driver A. Ground reference for secondary side A channel.
VSSB 9 P Ground for secondary-side driver B. Ground reference for secondary side B channel.
P =Power, I= Input, O= Output