ZHCSJ20C August   2018  – March 2019 UCC21530-Q1

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     功能方框图
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety-Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Propagation Delay and Pulse Width Distortion
    2. 7.2 Rising and Falling Time
    3. 7.3 Input and Enable Response Time
    4. 7.4 Programable Dead Time
    5. 7.5 Power-Up UVLO Delay to OUTPUT
    6. 7.6 CMTI Testing
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in UCC21530-Q1
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable Pin
      2. 8.4.2 Programmable Dead Time (DT) Pin
        1. 8.4.2.1 DT Pin Tied to VCC
        2. 8.4.2.2 DT Pin Connected to a Programming Resistor between DT and GND Pins
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing INA/INB Input Filter
        2. 9.2.2.2 Select Dead Time Resistor and Capacitor
        3. 9.2.2.3 Gate Driver Output Resistor
        4. 9.2.2.4 Estimate Gate Driver Power Loss
        5. 9.2.2.5 Estimating Junction Temperature
        6. 9.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 9.2.2.6.1 Selecting a VCCI Capacitor
        7. 9.2.2.7 Other Application Example Circuits
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Component Placement Considerations
      2. 11.1.2 Grounding Considerations
      3. 11.1.3 High-Voltage Considerations
      4. 11.1.4 Thermal Considerations
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 相关链接
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 术语表
  13. 13机械、封装和可订购信息
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information
      2. 13.1.2 Tape and Reel Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Electrical Characteristics

VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 15V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, DT pin tied to VCCI, CL = 0 pF, TA = –40°C to +125°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IVCCI VCCI quiescent current VINA = 0 V, VINB = 0 V 1.5 2.0 mA
IVDDA,
IVDDB
VDDA and VDDB quiescent current VINA = 0 V, VINB = 0 V 1.0 1.8 mA
IVCCI VCCI per operating current (f = 500 kHz) current per channel 2.0 mA
IVDDA,
IVDDB
VDDA and VDDB operating current (f = 500 kHz) current per channel, COUT = 100 pF,
VVDDA, VVDDB = 15 V
3.0 mA
VCCI TO GND UNDERVOLTAGE THRESHOLDS
VVCCI_ON UVLO Rising threshold 2.55 2.7 2.85 V
VVCCI_OFF UVLO Falling threshold 2.35 2.5 2.65 V
VVCCI_HYS UVLO Threshold hysteresis 0.2 V
VDD TO VSS UNDERVOLTAGE THRESHOLDS
VVDDA_ON,
VVDDB_ON
UVLO Rising threshold 12.5 13.5 14.5 V
VVDDA_OFF,
VVDDB_OFF
UVLO Falling threshold 11.5 12.5 13.5 V
VVDDA_HYS,
VVDDB_HYS
UVLO Threshold hysteresis 1.0 V
INA and INB
VINAH, VINBH Input high threshold voltage 1.6 1.8 2 V
VINAL, VINBL Input low threshold voltage 0.8 1 1.2 V
VINA_HYS, VINB_HYS Input threshold hysteresis 0.8 V
VINA, VINB Negative transient, ref to GND, 50 ns pulse Not production tested, bench test only –5 V
EN THRESHOLDS
VENH Enable high voltage 2.0 V
VENL Enable low voltage 0.8 V
OUTPUT
IOA+, IOB+ Peak output source current CVDD = 10 µF, CLOAD = 0.18 µF, f = 1 kHz, bench measurement 4 A
IOA-, IOB- Peak output sink current CVDD = 10 µF, CLOAD = 0.18 µF, f = 1 kHz, bench measurement 6 A
ROHA, ROHB Output resistance at high state IOUT = –10 mA, TA = 25°C, ROHA, ROHBdo not represent drive pull-up performance. See tRISE in Switching Characteristicsand Output Stage for details. 5 Ω
ROLA, ROLB Output resistance at low state IOUT = 10 mA, TA = 25°C 0.55 Ω
VOHA, VOHB Output voltage at high state VVDDA, VVDDB = 15 V, IOUT = –10 mA, TA = 25°C 14.95 V
VOLA, VOLB Output voltage at low state VVDDA, VVDDB = 15 V, IOUT = 10 mA, TA = 25°C 5.5 mV
DEADTIME AND OVERLAP PROGRAMMING
Dead time DT pin tied to VCCI Overlap determined by INA INB -
RDT = 20 kΩ 160 200 240 ns