SBVS038U Data sheet | 德州仪器 TI.com.cn

SBVS038U September 2003 – January 2015 TPS736

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

DCQ|6
- MPDS098D
DRB|8
- MPDS118K
DBV|5
- MPDS018S

散热焊盘机械数据 (封装 | 引脚)

DRB|8
- QFND058N

订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
Voltage	V_IN	–0.3	+6.0	V
	V_EN	–0.3	+6.0	V
	V_OUT	–0.3	+5.5	V
	V_NR, V_FB	–0.3	+6.0	V
Peak output current	I_OUT	Internally limited
Output short-circuit duration		Indefinite
Continuous total power dissipation	P_DISS	See Thermal Information
T_J	Junction temperature range	–55	150	°C
T_stg	Storage temperature range	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Electrical Characteristics Exposure to absolute maximum rated conditions for extended periods may affect device reliability

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_IN	Input supply voltage range	1.7	5.5	V
I_OUT	Output current	0	500	mA
T_J	Operating junction temperature	–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾⁽²⁾		TPS736⁽³⁾			UNIT
		DRB/SON	DCQ/SOT223	DBV/SOT23
		8 PINS	6 PINS	5 PINS
R_θJA	Junction-to-ambient thermal resistance⁽⁴⁾	52.8	118.7	221.9	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance⁽⁵⁾	60.4	64.9	74.9
R_θJB	Junction-to-board thermal resistance⁽⁶⁾	28.4	65.0	51.9
ψ_JT	Junction-to-top characterization parameter⁽⁷⁾	2.1	14.0	2.8
ψ_JB	Junction-to-board characterization parameter⁽⁸⁾	28.6	63.8	51.1
R_θJC(bot)	Junction-to-case (bottom) thermal resistance⁽⁹⁾	12.0	N/A	N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.

(3) Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations:

i. DRB: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array.
ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array.
iii. DBV: There is no exposed pad with the DBV package.
i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage.
ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
iii. DBV: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage.
These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To understand the effects of the copper area on thermal performance, see the Power Dissipation section of this data sheet.

(4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

(5) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(6) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.

(7) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain θ_JA using a procedure described in JESD51-2a (sections 6 and 7).

(8) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain θ_JA using a procedure described in JESD51-2a (sections 6 and 7).

(9) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

6.5 Electrical Characteristics

Over operating temperature range (T_J = –40°C to 125°C), V_IN = V_OUT(nom) + 0.5 V⁽¹⁾, I_OUT = 10 mA, V_EN = 1.7 V, and
C_OUT = 0.1 μF, unless otherwise noted. Typical values are at T_J = 25°C.

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IN	Input voltage range⁽¹⁾⁽²⁾			1.7		5.5	V
V_FB	Internal reference (TPS73601)		T_J = 25°C	1.198	1.20	1.210	V
V_OUT	Output voltage range (TPS73601)⁽³⁾			V_FB	5.5 – V_DO		V
	Accuracy⁽¹⁾⁽⁴⁾	Nominal	T_J = 25°C	–0.5		+0.5
	Accuracy⁽¹⁾⁽⁴⁾	over V_IN, I_OUT, and T	V_OUT + 0.5 V ≤ V_IN ≤ 5.5 V; 10 mA ≤ I_OUT ≤ 400 mA	–1.0%	±0.5%	+1.0%
ΔV_OUT(ΔVIN)	Line regulation⁽¹⁾		V_O(nom) + 0.5 V ≤ V_IN ≤ 5.5 V		0.01		%/V
ΔV_OUT(ΔIOUT)	Load regulation		1 mA ≤ I_OUT ≤ 400 mA		0.002		%/mA
ΔV_OUT(ΔIOUT)	Load regulation		10 mA ≤ I_OUT ≤ 400 mA		0.0005		%/mA
V_DO	Dropout voltage⁽⁵⁾ (V_IN = V_OUT(nom) – 0.1 V)		I_OUT = 400 mA		75	200	mV
Z_O(do)	Output impedance in dropout		1.7 V ≤ V_IN ≤ V_OUT + V_DO		0.25		Ω
I_CL	Output current limit		V_OUT = 0.9 × V_OUT(nom)	400	650	800	mA
I_CL	Output current limit		3.6 V ≤ V_IN ≤ 4.2 V, 0°C ≤ T_J ≤ 70°C	500		800	mA
I_SC	Short-circuit current		V_OUT = 0 V		450		mA
I_REV	Reverse leakage current⁽⁶⁾ (–I_IN)		V_EN ≤ 0.5 V, 0 V ≤ V_IN≤ V_OUT		0.1	10	μA
I_GND	GND pin current		I_OUT = 10 mA (I_Q)		400	550	μA
I_GND	GND pin current		I_OUT = 400 mA		800	1000	μA
I_SHDN	Shutdown current (I_GND)		V_EN ≤ 0.5 V, V_OUT ≤ V_IN ≤ 5.5, –40°C ≤ T_J ≤ 100°C		0.02	1	μA
I_FB	FB pin current (TPS73601)				0.1	0.3	μA
PSRR	Power-supply rejection ratio (ripple rejection)		f = 100 Hz, I_OUT = 400 mA		58		dB
PSRR	Power-supply rejection ratio (ripple rejection)		f = 10 kHz, I_OUT = 400 mA		37		dB
V_n	Output noise voltage BW = 10Hz – 100KHz		C_OUT = 10 μF, No C_NR		27 × V_OUT		μV_RMS
V_n	Output noise voltage BW = 10Hz – 100KHz		C_OUT = 10 μF, C_NR = 0.01 μF		8.5 × V_OUT		μV_RMS
t_STR	Startup time		V_OUT = 3 V, R_L = 30 Ω C_OUT = 1 μF, C_NR= 0.01 μF		600		μs
V_EN(high)	EN pin high (enabled)			1.7		V_IN	V
V_EN(low)	EN pin low (shutdown)			0		0.5	V
I_EN(high)	EN pin current (enabled)		V_EN = 5.5 V		0.02	0.1	μA
T_SD	Thermal shutdown temperature		Shutdown, temperature increasing		160		°C
T_SD	Thermal shutdown temperature		Reset, temperature decreasing		140		°C
T_J	Operating junction temperature			–40		125	°C

(1) Minimum V_IN = V_OUT + V_DO or 1.7 V, whichever is greater.

(2) For V_OUT(nom) < 1.6 V, when V_IN ≤ 1.6 V, the output locks to V_IN and may result in a damaging over-voltage level on the output. To avoid this situation, disable the device before powering down the V_IN.

(3) TPS73601 is tested at V_OUT = 2.5 V.

(4) Tolerance of external resistors not included in this specification.

(5) V_DO is not measured for fixed output versions with V_OUT(nom) < 1.8 V.

(6) Fixed-voltage versions only; refer to Application Information section for more information.