ZHCSI09S June 2010 – August 2018 TPS65911
Figure 5-2 shows the device state control through PWRON signal.
Table 5-4 lists the power control timing characteristics.
|tdbPWRONF||PWRON falling-edge debouncing delay||100||ms|
|tdbPWRONR||PWRON rising-edge debouncing delay||3 × tCK32k = 94||µs|
|tdbPWRHOLD||PWRHOLD rising-edge debouncing delay||2 × tCK32k = 63||µs|
|tdOINT1||INT1 (internal) power-on pulse duration after PWRON low-level (debounced) event||1||s|
|tdONPWHOLD||Delay to set high PWRHOLD signal or DEV_ON control bit after NRESPWON released to keep on the supplies||tdOINT1 – tDSONT = 970(1)||ms|
|tdPWRONLP||PWRON long-press delay||PWRON falling-edge to PWRON_LP_IT||4||s|
|tdPWRONLPTO||PWROW long-press interrupt (PWRON_LP_IT) to supplies switch-off||PWRON_LP_IT to NRESPWRON falling-edge||1||s|