ZHCSI09S June   2010  – August 2018 TPS65911

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison Table
  4. 4Pin Configuration and Functions
    1. 4.1 Pin Attributes
      1.      Pin Attributes
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: I/O Pullup and Pulldown
    6. 5.6  Electrical Characteristics: Digital I/O Voltage
    7. 5.7  Electrical Characteristics: Power Consumption
    8. 5.8  Electrical Characteristics: Power References and Thresholds
    9. 5.9  Electrical Characteristics: Thermal Monitoring and Shutdown
    10. 5.10 Electrical Characteristics: 32-kHz RTC Clock
    11. 5.11 Electrical Characteristics: Backup Battery Charger
    12. 5.12 Electrical Characteristics: VRTC LDO
    13. 5.13 Electrical Characteristics: VIO SMPS
    14. 5.14 Electrical Characteristics: VDD1 SMPS
    15. 5.15 Electrical Characteristics: VDD2 SMPS
    16. 5.16 Electrical Characteristics: VDDCtrl SMPS
    17. 5.17 Electrical Characteristics: LDO1 and LDO2
    18. 5.18 Electrical Characteristics: LDO3 and LDO4
    19. 5.19 Electrical Characteristics: LDO5
    20. 5.20 Electrical Characteristics: LDO6, LDO7, and LDO8
    21. 5.21 Timing and Switching Characteristics
      1. 5.21.1 I2C Timing and Switching
      2. 5.21.2 Switch-ON and Switch-OFF Sequences and Timing
      3. 5.21.3 Power Control Timing
        1. 5.21.3.1 Device State Control Through PWRON Signal
        2. 5.21.3.2 Device SLEEP State Control
        3. 5.21.3.3 Device Turnon and Turnoff With Rising and Falling Input Voltage
        4. 5.21.3.4 Power Supplies State Control Through EN1 and EN2 Signals
        5. 5.21.3.5 VDD1, VDD2 Voltage Control Through EN1 and EN2 Signals
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Power Reference
    4. 6.4  Power Resources
    5. 6.5  Embedded Power Controller (EPC)
      1. 6.5.1 State Machine
        1. 6.5.1.1 Device POWER ON Enable Conditions
        2. 6.5.1.2 Device POWER ON Disable Conditions
        3. 6.5.1.3 Device SLEEP Enable Conditions
        4. 6.5.1.4 Device Reset Scenarios
      2. 6.5.2 BOOT Configuration, Switch-ON, and Switch-OFF Sequences
      3. 6.5.3 Control Signals
        1. 6.5.3.1  SLEEP
        2. 6.5.3.2  PWRHOLD
        3. 6.5.3.3  BOOT1
        4. 6.5.3.4  NRESPWRON, NRESPWRON2
        5. 6.5.3.5  CLK32KOUT
        6. 6.5.3.6  PWRON
        7. 6.5.3.7  INT1
        8. 6.5.3.8  EN2 and EN1
        9. 6.5.3.9  GPIO0 to GPIO8
        10. 6.5.3.10 HDRST Input
        11. 6.5.3.11 PWRDN
        12. 6.5.3.12 Comparators: COMP1 and COMP2
        13. 6.5.3.13 Watchdog
        14. 6.5.3.14 Tracking LDO
    6. 6.6  PWM and LED Generators
    7. 6.7  Dynamic Voltage Frequency Scaling and Adaptive Voltage Scaling Operation
    8. 6.8  32-kHz RTC Clock
    9. 6.9  Real Time Clock (RTC)
      1. 6.9.1 Time Calendar Registers
      2. 6.9.2 General Registers
      3. 6.9.3 Compensation Registers
    10. 6.10 Backup Battery Management
    11. 6.11 Backup Registers
    12. 6.12 I2C Interface
      1. 6.12.1 Access Protocols
        1. 6.12.1.1 Single Byte Access
        2. 6.12.1.2 Multiple Byte Access to Several Adjacent Registers
    13. 6.13 Thermal Monitoring and Shutdown
    14. 6.14 Interrupts
    15. 6.15 Register Maps
      1. 6.15.1 Functional Registers
        1. 6.15.1.1 TPS65911_FUNC_REG Registers Mapping Summary
        2. 6.15.1.2 TPS65911_FUNC_REG Register Descriptions
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 External Component Recommendation
        2. 7.2.2.2 Controller Design Procedure
          1. 7.2.2.2.1 Inductor Selection
          2. 7.2.2.2.2 Selecting the RTRIP Resistor
          3. 7.2.2.2.3 Selecting the Output Capacitors
          4. 7.2.2.2.4 Selecting FETs
          5. 7.2.2.2.5 Bootstrap Capacitor
          6. 7.2.2.2.6 Selecting Input Capacitors
        3. 7.2.2.3 Converter Design Procedure
          1. 7.2.2.3.1 Selecting the Inductor
          2. 7.2.2.3.2 Selecting Output Capacitors
          3. 7.2.2.3.3 Selecting Input Capacitors
      3. 7.2.3 Application Curves
      4. 7.2.4 Layout Guidelines
        1. 7.2.4.1 PCB Layout
      5. 7.2.5 Layout Example
    3. 7.3 Power Supply Recommendations
  8. 8器件和文档支持
    1. 8.1 器件支持
      1. 8.1.1 开发支持
      2. 8.1.2 器件命名规则
    2. 8.2 文档支持
      1. 8.2.1 相关文档
    3. 8.3 接收文档更新通知
    4. 8.4 社区资源
      1. 8.4.1 社区资源
    5. 8.5 商标
    6. 8.6 静电放电警告
    7. 8.7 术语表
  9. 9机械、封装和可订购信息
    1. 9.1 封装 说明

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5.16 Electrical Characteristics: VDDCtrl SMPS

Over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage for external FETs 3 25 V
Input voltage V5IN 4.5 5.5 V
VOUT DC output voltage IOUT = 0 to IOUTmax: maximum programmable voltage SEL[6:0] = 1000011 to 1111111 1.4 V
...
SEL[6:0] = 0110001 1.2
...
IOUT = 0 to IOUTmax: minimum programmable voltage SEL[6:0] = 0000001 to 0000011 0.6
SEL[6:0] = 000000: power down 0
VOUTSTEP DC output voltage programmable step 12.5 mV
ton Turnon time, off to on From EN high to Vout = 95% 900 µs
Output voltage transition rate From VOUT = 0.6 V to 1.4 V and VOUT = 1.4 V to 0.6 V IOUT = 500 mA 5(1) mV/µs
Switching frequency IOUT = 100 mA 10 kHz
IOUT = 1 A 100
IOUT = 5 A 340
IQ Ground current, off 1 µA
Ground current, no load 400 500
SUPPLY CURRENT
I(V5IN) V5IN supply current V5IN current, TA = 25°C,
No load
V(EN) = 5 V,
V(VOUT) = 0.63 V		 320 500 µA
ISD(V5IN) V5IN shutdown current V5IN current,
TA = 25°C,
No load,
V(EN) = 0 V		 1 µA
INTERNAL REFERENCE VOLTAGE
Reference 0.5974 0.603 0.6086 V
Mismatch of resistive divider Specified by design. Not production tested. (–0.0063 × VOUT + 0.0035)% VOUT% 0.001 × VOUT – 0.0003%
I(VOUT) Output current Specified by design. Not production tested.
I(VOUT) = 10–4 × VOUT – 6 × 10–5 		VOUT = 0.6 V 1.25 µA
... ...
VOUT = 1 V 40
... ...
VOUT = 1.3875 V 78.75
OUTPUT DISCHARGE
IDischg Output discharge current from SW pin V(EN) = 0 V, V(SW) = 0.5 V 5 13 mA
OUTPUT DRIVERS
R(DRVH) DRVH resistance Source, I(DRVH) = –50 mA 1.5 3 Ω
Sink, I(DRVH) = 50 mA 0.7 1.8
R(DRVL) DRVL resistance Source, I(DRVL) = –50 mA 1 2.2
Sink, I(DRVL) = 50 mA 0.5 1.2
tD Dead time DRVH-off to DRVL-on 7 17 30 ns
DRVH-off to DRVL-on 10 22 35
BOOT STRAP SWITCH
V(FBST) Forward voltage V(V5IN-VBST), IF = 10 mA, TA = 25°C 0.1 0.2 V
Ilkg VBST leakage current V(VBST) = 34.5 V, V(SW) = 28 V, TA = 25°C 0.01 1.5 µA
DUTY AND FREQUENCY CONTROL
tOFF(min) Minimum off-time TA = 25°C 150 260 400 ns
tON(min) Minimum on-time VIN = 28 V, VOUT = 0.6 V, TA = 25°C
Specified by design. Not production tested.		 86
fSW Switching frequency TA = 25°C 312 340 368 kHz
SOFTSTART
tss Internal SS time From V(EN) = high to VOUT = 95% 0.9 ms
PROTECTION: CURRENT SENSE
V(TRIP) TRIP source current V(TRIP) = 1 V, TA = 25°C 9 10 11 µA
TRIP current temperature coefficient On the basis of 25°C 4700 ppm/°C
V(TRIP) Current limit threshold setting range V(TRIP-GND) Voltage 0.2 3 V
VOCL Current limit threshold V(TRIP) = 3 V 355 375 395 mV
V(TRIP) = 1.6 V 185 200 215
V(TRIP) = 0.2 V 17 25 33
VOCLN Negative current limit threshold V(TRIP) = 3 V –395 –375 –355 mV
V(TRIP) = 1.6 V –215 –200 –185
V(TRIP) = 0.2 V –33 –25 –17
Auto zero cross adjustable range Positive 3 15 mV
Negative –15 –3
UVLO
V5IN UVLO threshold Wake up 4.2 4.38 4.5 V
Shutdown 3.7 3.93 4.1
THERMAL SHUTDOWN
TSDN Thermal shutdown threshold Shutdown temperature
Specified by design. Not production tested.		 145 °C
Hysteresis
Specified by design. Not production tested.		 10
(1) The output voltage is changed with 50 mV/10 µs steps