ZHCSIX2 October   2018 TPS65216

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 简化原理图
  2. 2Pin Configuration and Functions
    1. 2.1 Pin Functions
      1.      Pin Functions
  3. 3Specifications
    1. 3.1 Absolute Maximum Ratings
    2. 3.2 ESD Ratings
    3. 3.3 Recommended Operating Conditions
    4. 3.4 Thermal Information
    5. 3.5 Electrical Characteristics
    6. 3.6 Timing Requirements
    7. 3.7 Typical Characteristics
  4. 4Detailed Description
    1. 4.1 Overview
    2. 4.2 Functional Block Diagram
    3. 4.3 Feature Description
      1. 4.3.1 Wake-Up and Power-Up and Power-Down Sequencing
        1. 4.3.1.1  Power-Up Sequencing
        2. 4.3.1.2  Power-Down Sequencing
        3. 4.3.1.3  Strobes 1 and 2
        4. 4.3.1.4  Supply Voltage Supervisor and Power Good (PGOOD)
        5. 4.3.1.5  Internal LDO (INT_LDO)
        6. 4.3.1.6  Current Limited Load Switch
        7. 4.3.1.7  LDO1
        8. 4.3.1.8  UVLO
        9. 4.3.1.9  Power-Fail Comparator
        10. 4.3.1.10 DCDC3 / DCDC4 Power-Up Default Selection
        11. 4.3.1.11 I/O Configuration
          1. 4.3.1.11.1 Using GPIO2 as Reset Signal to DCDC1 and DCDC2
        12. 4.3.1.12 Push Button Input (PB)
          1. 4.3.1.12.1 Signaling PB-Low Event on the nWAKEUP Pin
          2. 4.3.1.12.2 Push Button Reset
        13. 4.3.1.13 AC_DET Input (AC_DET)
        14. 4.3.1.14 Interrupt Pin (INT)
        15. 4.3.1.15 I2C Bus Operation
    4. 4.4 Device Functional Modes
      1. 4.4.1 Modes of Operation
      2. 4.4.2 OFF
      3. 4.4.3 ACTIVE
      4. 4.4.4 SUSPEND
      5. 4.4.5 RESET
    5. 4.5 Register Maps
      1. 4.5.1 Password Protection
      2. 4.5.2 FLAG Register
      3. 4.5.3 TPS65216Registers
        1. 4.5.3.1  CHIPID Register (subaddress = 0x0) [reset = 0x5]
          1. Table 4-7 CHIPID Register Field Descriptions
        2. 4.5.3.2  INT1 Register (subaddress = 0x1) [reset = 0x0]
          1. Table 4-8 INT1 Register Field Descriptions
        3. 4.5.3.3  INT2 Register (subaddress = 0x2) [reset = 0x0]
          1. Table 4-9 INT2 Register Field Descriptions
        4. 4.5.3.4  INT_MASK1 Register (subaddress = 0x3) [reset = 0x0]
          1. Table 4-10 INT_MASK1 Register Field Descriptions
        5. 4.5.3.5  INT_MASK2 Register (subaddress = 0x4) [reset = 0x0]
          1. Table 4-11 INT_MASK2 Register Field Descriptions
        6. 4.5.3.6  STATUS Register (subaddress = 0x5) [reset = 00XXXXXXb]
          1. Table 4-12 STATUS Register Field Descriptions
        7. 4.5.3.7  CONTROL Register (subaddress = 0x6) [reset = 0x0]
          1. Table 4-13 CONTROL Register Field Descriptions
        8. 4.5.3.8  FLAG Register (subaddress = 0x7) [reset = 0x0]
          1. Table 4-14 FLAG Register Field Descriptions
        9. 4.5.3.9  PASSWORD Register (subaddress = 0x10) [reset = 0x0]
          1. Table 4-15 PASSWORD Register Field Descriptions
        10. 4.5.3.10 ENABLE1 Register (subaddress = 0x11) [reset = 0x0]
          1. Table 4-16 ENABLE1 Register Field Descriptions
        11. 4.5.3.11 ENABLE2 Register (subaddress = 0x12) [reset = 0x0]
          1. Table 4-17 ENABLE2 Register Field Descriptions
        12. 4.5.3.12 CONFIG1 Register (subaddress = 0x13) [reset = 0x4C]
          1. Table 4-18 CONFIG1 Register Field Descriptions
        13. 4.5.3.13 CONFIG2 Register (subaddress = 0x14) [reset = 0xC0]
          1. Table 4-19 CONFIG2 Register Field Descriptions
        14. 4.5.3.14 CONFIG3 Register (subaddress = 0x15) [reset = 0x0]
          1. Table 4-20 CONFIG3 Register Field Descriptions
        15. 4.5.3.15 DCDC1 Register (offset = 0x16) [reset = 0x99]
          1. Table 4-21 DCDC1 Register Field Descriptions
        16. 4.5.3.16 DCDC2 Register (subaddress = 0x17) [reset = 0x99]
          1. Table 4-22 DCDC2 Register Field Descriptions
        17. 4.5.3.17 DCDC3 Register (subaddress = 0x18) [reset = 0x8C]
          1. Table 4-23 DCDC3 Register Field Descriptions
        18. 4.5.3.18 DCDC4 Register (subaddress = 0x19) [reset = 0xB2]
          1. Table 4-24 DCDC4 Register Field Descriptions
        19. 4.5.3.19 SLEW Register (subaddress = 0x1A) [reset = 0x6]
          1. Table 4-25 SLEW Register Field Descriptions
        20. 4.5.3.20 LDO1 Register (subaddress = 0x1B) [reset = 0x1F]
          1. Table 4-26 LDO1 Register Field Descriptions
        21. 4.5.3.21 SEQ1 Register (subaddress = 0x20) [reset = 0x0]
          1. Table 4-27 SEQ1 Register Field Descriptions
        22. 4.5.3.22 SEQ2 Register (subaddress = 0x21) [reset = 0x0]
          1. Table 4-28 SEQ2 Register Field Descriptions
        23. 4.5.3.23 SEQ3 Register (subaddress = 0x22) [reset = 0x98]
          1. Table 4-29 SEQ3 Register Field Descriptions
        24. 4.5.3.24 SEQ4 Register (subaddress = 0x23) [reset = 0x75]
          1. Table 4-30 SEQ4 Register Field Descriptions
        25. 4.5.3.25 SEQ5 Register (subaddress = 0x24) [reset = 0x12]
          1. Table 4-31 SEQ5 Register Field Descriptions
        26. 4.5.3.26 SEQ6 Register (subaddress = 0x25) [reset = 0x63]
          1. Table 4-32 SEQ6 Register Field Descriptions
        27. 4.5.3.27 SEQ7 Register (subaddress = 0x26) [reset = 0x3]
          1. Table 4-33 SEQ7 Register Field Descriptions
  5. 5Application and Implementation
    1. 5.1 Application Information
    2. 5.2 Typical Application
      1. 5.2.1 Design Requirements
      2. 5.2.2 Detailed Design Procedure
        1. 5.2.2.1 Output Filter Design
        2. 5.2.2.2 Inductor Selection for Buck Converters
        3. 5.2.2.3 Output Capacitor Selection
      3. 5.2.3 Application Curves
  6. 6Power Supply Recommendations
  7. 7Layout
    1. 7.1 Layout Guidelines
    2. 7.2 Layout Example
  8. 8器件和文档支持
    1. 8.1 器件支持
      1. 8.1.1 第三方产品免责声明
    2. 8.2 文档支持
      1. 8.2.1 相关文档
    3. 8.3 接收文档更新通知
    4. 8.4 社区资源
    5. 8.5 商标
    6. 8.6 静电放电警告
    7. 8.7 Glossary
  9. 9机械、封装和可订购信息
    1. 9.1 Package Option Addendum
      1. 9.1.1 Packaging Information
      2. 9.1.2 Tape and Reel Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

4.5.3.15 DCDC1 Register (offset = 0x16) [reset = 0x99]

DCDC1 is shown in Figure 4-39 and described in Table 4-21.

Return to Summary Table.

Note 1: This register is password protected. For more information, see Section 4.5.1.
Note 2: A 5-ms blanking time of the overvoltage and undervoltage monitoring occurs when a write is performed on the DCDC1 register.
Note 3: To change the output voltage of DCDC1, the GO bit or the GODSBL bit must be set to 1b in register 0x1A.

Figure 4-39 DCDC1 Register
7 6 5 4 3 2 1 0
PFM RESERVED DCDC1
R/W-1b R-0b R/W-19h

Table 4-21 DCDC1 Register Field Descriptions

Bit Field Type Reset Description
7 PFM R/W 1b

Pulse Frequency Modulation (PFM, also known as pulse-skip-mode) enable. PFM mode improves light-load efficiency. Actual PFM mode operation depends on load condition.

0b = Disabled (forced PWM)

1b = Enabled

6 RESERVED R 0b

5-0 DCDC1 R/W, E2 19h

DCDC1 output voltage setting

0h = 0.850

1h = 0.860

2h = 0.870

3h = 0.880

4h = 0.890

5h = 0.900

6h = 0.910

7h = 0.920

8h = 0.930

9h = 0.940

Ah = 0.950

Bh = 0.960

Ch = 0.970

Dh = 0.980

Eh = 0.990

Fh = 1.000

10h = 1.010

11h = 1.020

12h = 1.030

13h = 1.040

14h = 1.050

15h = 1.060

16h = 1.070

17h = 1.080

18h = 1.090

19h = 1.100

1Ah = 1.110

1Bh = 1.120

1Ch = 1.130

1Dh = 1.140

1Eh = 1.150

1Fh = 1.160

20h = 1.170

21h = 1.180

22h = 1.190

23h = 1.200

24h = 1.210

25h = 1.220

26h = 1.230

27h = 1.240

28h = 1.250

29h = 1.260

2Ah = 1.270

2Bh = 1.280

2Ch = 1.290

2Dh = 1.300

2Eh = 1.310

2Fh = 1.320

30h = 1.330

31h = 1.340

32h = 1.350

33h = 1.375

34h = 1.400

35h = 1.425

36h = 1.450

37h = 1.475

38h = 1.500

39h = 1.525

3Ah = 1.550

3Bh = 1.575

3Ch = 1.600

3Dh = 1.625

3Eh = 1.650

3Fh = 1.675