ZHCSIX2 October 2018 TPS65216
PRODUCTION DATA.
CONFIG1 is shown in Figure 4-36 and described in Table 4-18.
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TRST | RESERVED | RESERVED | PGDLY | STRICT | UVLO | ||
R/W-0b | R/W-1b | R/W-0b | R/W-1h | R/W-1b | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | TRST | R/W, E2 | 0b |
Push-button reset time constant 0b = 8s 1b = 15s |
6 | RESERVED | R/W | 1b |
|
5 | RESERVED | R/W | 0b |
|
4-3 | PGDLY | R/W, E2 | 1h |
Power-Good delay. Note: Power-good delay applies to rising-edge only (power-up), not falling edge (power-down or fault) 0h = 10 ms 1h = 20 ms 2h = 50 ms 3h = 150 ms |
2 | STRICT | R/W, E2 | 1b |
Supply Voltage Supervisor Sensitivity selection. See Section 3.5 for details. 0b = Power-good threshold (VOUT falling) has wider limits. Overvoltage is not monitored 1b = Power-good threshold (VOUT falling) has tight limits. Overvoltage is monitored. |
1-0 | UVLO | R/W, E2 | 0h |
UVLO setting 0h = 2.75 V 1h = 2.95 V 2h = 3.25 V 3h = 3.35 V |