ZHCSGZ6 October   2017 TPS6508700

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能框图
  2. 2修订历史记录
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Functions
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  Electrical Characteristics: Total Current Consumption
    6. 4.6  Electrical Characteristics: Reference and Monitoring System
    7. 4.7  Electrical Characteristics: Buck Controllers
    8. 4.8  Electrical Characteristics: Synchronous Buck Converters
    9. 4.9  Electrical Characteristics: LDOs
    10. 4.10 Electrical Characteristics: Load Switches
    11. 4.11 Digital Signals: I2C Interface
    12. 4.12 Digital Input Signals (CTLx)
    13. 4.13 Digital Output Signals (IRQB, GPOx)
    14. 4.14 Timing Requirements
    15. 4.15 Switching Characteristics
    16. 4.16 Typical Characteristics
  5. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 SMPS Voltage Regulators
      1. 5.3.1 Controller Overview
      2. 5.3.2 Converter Overview
      3. 5.3.3 Dynamic Voltage Scaling
      4. 5.3.4 Current Limit
    4. 5.4 LDO Regulators and Load Switches
      1. 5.4.1 VTT LDO
      2. 5.4.2 LDOA1-LDOA3
      3. 5.4.3 Load Switches
    5. 5.5 Power Good Information (PGOOD or PG) and GPO Pins
    6. 5.6 Power Sequencing and Voltage-Rail Control
      1. 5.6.1 Power-Up and Power-Down Sequencing
      2. 5.6.2 Emergency Shutdown
    7. 5.7 Device Functional Modes
      1. 5.7.1 Off Mode
      2. 5.7.2 Standby Mode
      3. 5.7.3 Active Mode
    8. 5.8 I2C Interface
      1. 5.8.1 F/S-Mode Protocol
    9. 5.9 Register Maps
      1. 5.9.1  Register Map Summary
      2. 5.9.2  DEVICEID: PMIC Device and Revision ID Register (offset = 1h) [reset = 10h]
      3. 5.9.3  IRQ: PMIC Interrupt Register (offset = 2h) [reset = 0h]
      4. 5.9.4  IRQ_MASK: PMIC Interrupt Mask Register (offset = 3h) [reset = FFh]
      5. 5.9.5  PMICSTAT: PMIC Status Register (offset = 4h) [reset = 0h]
      6. 5.9.6  SHUTDNSRC: PMIC Shut-Down Event Register (offset = 5h) [reset = 0h]
      7. 5.9.7  BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = 50h]
      8. 5.9.8  BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = 70h]
      9. 5.9.9  BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = 70h]
      10. 5.9.10 BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = 70h]
      11. 5.9.11 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = Dh]
      12. 5.9.12 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = Dh]
      13. 5.9.13 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = Dh]
      14. 5.9.14 LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = Ch]
      15. 5.9.15 LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = 3Ch]
      16. 5.9.16 DISCHCTRL1: Discharge Control1 Register (offset = 40h) [reset = 55h]
      17. 5.9.17 DISCHCTRL2: Discharge Control2 Register (offset = 41h) [reset = 55h]
      18. 5.9.18 DISCHCTRL3: Discharge Control3 Register (offset = 42h) [reset = 15h]
      19. 5.9.19 PG_DELAY1: Power Good Delay1 Register (offset = 43h) [reset = 0h]
      20. 5.9.20 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0h]
      21. 5.9.21 BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = 50h]
      22. 5.9.22 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = 20h]
      23. 5.9.23 BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = 20h]
      24. 5.9.24 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = 70h]
      25. 5.9.25 BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = E8h]
      26. 5.9.26 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = E8h]
      27. 5.9.27 BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = E8h]
      28. 5.9.28 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = FFh]
      29. 5.9.29 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = AAh]
      30. 5.9.30 BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = 7h]
      31. 5.9.31 PG_DELAY2: Power Good Delay2 Register (offset = 9Dh) [reset = 21h]
      32. 5.9.32 SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = 0h]
      33. 5.9.33 I2C_RAIL_EN1: VR Pin Enable Override1 Register (offset = A0h) [reset = 80h]
      34. 5.9.34 I2C_RAIL_EN2/GPOCTRL: VR Pin Enable Override2/GPO Control Register (offset = A1h) [reset = 89h]
      35. 5.9.35 PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = C0h]
      36. 5.9.36 PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = 3Fh]
      37. 5.9.37 GPO1PG_CTRL1: GPO1 PG Control1 Register (offset = A4h) [reset = C2h]
      38. 5.9.38 GPO1PG_CTRL2: GPO1 PG Control2 Register (offset = A5h) [reset = AFh]
      39. 5.9.39 GPO4PG_CTRL1: GPO4 PG Control1 Register (offset = A6h) [reset = 0h]
      40. 5.9.40 GPO4PG_CTRL2: GPO4 PG Control2 Register (offset = A7h) [reset = 0h]
      41. 5.9.41 GPO2PG_CTRL1: GPO2 PG Control1 Register (offset = A8h) [reset = C0h]
      42. 5.9.42 GPO2PG_CTRL2: GPO2 PG Control2 Register (offset = A9h) [reset = 2Fh]
      43. 5.9.43 GPO3PG_CTRL1: GPO3 PG Control1 Register (offset = AAh) [reset = 0h]
      44. 5.9.44 GPO3PG_CTRL2: GPO3 PG Control2 Register (offset = ABh) [reset = 0h]
      45. 5.9.45 MISCSYSPG Register (offset = ACh) [reset = FFh]
      46. 5.9.46 LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = 7Dh]
      47. 5.9.47 PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0h]
      48. 5.9.48 PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0h]
      49. 5.9.49 PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0h]
      50. 5.9.50 PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0h]
      51. 5.9.51 TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0h]
      52. 5.9.52 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0h]
      53. 5.9.53 OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0h]
  6. 6Applications, Implementation, and Layout
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 Controller Design Procedure
          1. 6.2.2.1.1 Controller With External Feedback Resistor
          2. 6.2.2.1.2 Selecting the Inductor
          3. 6.2.2.1.3 Selecting the Output Capacitors
          4. 6.2.2.1.4 Selecting the FETs
          5. 6.2.2.1.5 Bootstrap Capacitor
          6. 6.2.2.1.6 Setting the Current Limit
          7. 6.2.2.1.7 Selecting the Input Capacitors
        2. 6.2.2.2 Converter Design Procedure
          1. 6.2.2.2.1 Selecting the Inductor
          2. 6.2.2.2.2 Selecting the Output Capacitors
          3. 6.2.2.2.3 Selecting the Input Capacitors
        3. 6.2.2.3 LDO Design Procedure
      3. 6.2.3 Application Curves
      4. 6.2.4 Layout
        1. 6.2.4.1 Layout Guidelines
        2. 6.2.4.2 Layout Example
    3. 6.3 Power Supply Coupling and Bulk Capacitors
    4. 6.4 Do's and Don'ts
  7. 7器件和文档支持
    1. 7.1 器件支持
      1. 7.1.1 第三方产品免责声明
    2. 7.2 文档支持
      1. 7.2.1 相关文档
    3. 7.3 接收文档更新通知
    4. 7.4 社区资源
    5. 7.5 商标
    6. 7.6 静电放电警告
    7. 7.7 术语表
  8. 8机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RSK|64
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Detailed Description

5.1 Overview

The TPS6508700 power-management integrated circuit (PMIC) provides all the required power supplies for the AMD Family 17h Models 10h-1Fh Processors. The PMIC has the following integrated components: three step-down controllers (BUCK1, BUCK2, and BUCK6), three step-down converters (BUCK3, BUCK4, and BUCK5), a sink or source LDO (VTT LDO), three low-voltage VIN LDOs (LDOA1–LDOA3), and three load switches (SWA1, SWB1, and SWB2). With on-chip, one-time programmable (OTP) memory, configuration of each rail for the default output value, power-up sequence, fault handling, and power good mapping into a GPO pin are all conveniently flexible. All voltage rails (VRs) have a built-in discharge resistor, and the value can be changed using the DISCHCNT1–DISCHCNT3 and LDOA1_CTRL registers. When enabling a VR, the PMIC automatically disconnects the discharge resistor for that rail without any I2C command. Table 5-1 lists the key characteristics of the voltage rails.

Table 5-1 Summary of Voltage Regulators

RAIL TYPE INPUT VOLTAGE (V) OUTPUT VOLTAGE RANGE (V) CURRENT (mA)
MIN MAX MIN TYP MAX
BUCK1 Step-down controller 4.5 21 5 V by external feedback Scalable
BUCK2 Step-down controller 4.5 21 0.41 0.8 1.67 Scalable
BUCK3 Step-down converter 4.5 5.5 0.425 1.8 3.575 3000
BUCK4 Step-down converter 4.5 5.5 0.425 0.8 3.575 3000
BUCK5 Step-down converter 4.5 5.5 0.425 1.8 3.575 3000
BUCK6 Step-down controller 4.5 21 1 3.3 3.575 Scalable
LDOA1 LDO 4.5 5.5 1.35 3.3 3.3 200(1)
LDOA2 LDO 1.62 1.98 0.7 1.5 1.5 600
LDOA3 LDO 1.62 1.98 0.7 1.2 1.5 600
SWA1 Load switch 0.5 3.3 1.5 300
SWB1/SWB2 Load switch 0.5 3.3 1.5 300
VTT Sink and Source LDO BUCK6 output VBUCK6 / 2
(1) When powered from a 5-V supply through the DRV5V_2_A1 pin. Otherwise, max current is limited by max IOUT of LDO5.

5.2 Functional Block Diagram

TPS6508700 BlockDiagram.gif Figure 5-1 PMIC Functional Block Diagram

5.3 SMPS Voltage Regulators

The buck controllers integrate gate drivers for external power stages with a programmable current limit (set by an external resistor at ILIMx pin), which allows for optimal selection of external passive components based on the desired system load. The buck converters include an integrated power stage and require a minimum number of pins for power input, inductor, and output voltage feedback input. Combined with high-frequency switching, all these features allow the use of inductors in a small form factor, reducing total-system cost and size.

BUCK1–BUCK6 have selectable auto-PWM and forced-PWM mode through the BUCKx_MODE bit in the BUCKxCTRL register. In default auto-PWM mode, the VR automatically switches between pulse width modulation (PWM) and pulse frequency modulation (PFM) depending on the output load to maximize efficiency.

All controllers and converters can be set to the default output voltage (VOUT) or dynamically voltage changing at any time. This feature means that the rails can be programmed for any VOUT by the factory, therefore the device starts up with the default voltage, or during operation the rail can be programmed to another operating VOUT while the rail is enable or disabled. Two step sizes, or ranges, are available for VOUT selection: 10-mV steps and 25-mV steps. The step-size range must be selected prior to use and must be programmed by the factory. The step-size range is not subject to programming or change during operation.

Table 5-2 lists the options for the 10-mV step-size range VOUT. Table 5-3 lists the options for the 25-mV step-size range VOUT.

Table 5-2 10-mV Step-Size VOUT Range

VID BITS VOUT VID BITS VOUT VID BITS VOUT
0000000b 0 0101011b 0.83 1010110b 1.26
0000001b 0.41 0101100b 0.84 1010111b 1.27
0000010b 0.42 0101101b 0.85 1011000b 1.28
0000011b 0.43 0101110b 0.86 1011001b 1.29
0000100b 0.44 0101111b 0.87 1011010b 1.30
0000101b 0.45 0110000b 0.88 1011011b 1.31
0000110b 0.46 0110001b 0.89 1011100b 1.32
0000111b 0.47 0110010b 0.90 1011101b 1.33
0001000b 0.48 0110011b 0.91 1011110b 1.34
0001001b 0.49 0110100b 0.92 1011111b 1.35
0001010b 0.50 0110101b 0.93 1100000b 1.36
0001011b 0.51 0110110b 0.94 1100001b 1.37
0001100b 0.52 0110111b 0.95 1100010b 1.38
0001101b 0.53 0111000b 0.96 1100011b 1.39
0001110b 0.54 0111001b 0.97 1100100b 1.40
0001111b 0.55 0111010b 0.98 1100101b 1.41
0010000b 0.56 0111011b 0.99 1100110b 1.42
0010001b 0.57 0111100b 1.00 1100111b 1.43
0010010b 0.58 0111101b 1.01 1101000b 1.44
0010011b 0.59 0111110b 1.02 1101001b 1.45
0010100b 0.60 0111111b 1.03 1101010b 1.46
0010101b 0.61 1000000b 1.04 1101011b 1.47
0010110b 0.62 1000001b 1.05 1101100b 1.48
0010111b 0.63 1000010b 1.06 1101101b 1.49
0011000b 0.64 1000011b 1.07 1101110b 1.50
0011001b 0.65 1000100b 1.08 1101111b 1.51
0011010b 0.66 1000101b 1.09 1110000b 1.52
0011011b 0.67 1000110b 1.10 1110001b 1.53
0011100b 0.68 1000111b 1.11 1110010b 1.54
0011101b 0.69 1001000b 1.12 1110011b 1.55
0011110b 0.70 1001001b 1.13 1110100b 1.56
0011111b 0.71 1001010b 1.14 1110101b 1.57
0100000b 0.72 1001011b 1.15 1110110b 1.58
0100001b 0.73 1001100b 1.16 1110111b 1.59
0100010b 0.74 1001101b 1.17 1111000b 1.60
0100011b 0.75 1001110b 1.18 1111001b 1.61
0100100b 0.76 1001111b 1.19 1111010b 1.62
0100101b 0.77 1010000b 1.20 1111011b 1.63
0100110b 0.78 1010001b 1.21 1111100b 1.64
0100111b 0.79 1010010b 1.22 1111101b 1.65
0101000b 0.80 1010011b 1.23 1111110b 1.66
0101001b 0.81 1010100b 1.24 1111111b 1.67
0101010b 0.82 1010101b 1.25 — —

Table 5-3 25-mV Step-Size VOUT Range

VID BITS VOUT (Converters) VOUT (Controllers) VID BITS VOUT VID BITS VOUT
0000000b 0 1.000 0101011b 1.475 1010110b 2.550
0000001b 0.425 1.000 0101100b 1.500 1010111b 2.575
0000010b 0.450 1.000 0101101b 1.525 1011000b 2.600
0000011b 0.475 1.000 0101110b 1.550 1011001b 2.625
0000100b 0.500 1.000 0101111b 1.575 1011010b 2.650
0000101b 0.525 1.000 0110000b 1.600 1011011b 2.675
0000110b 0.550 1.000 0110001b 1.625 1011100b 2.700
0000111b 0.575 1.000 0110010b 1.650 1011101b 2.725
0001000b 0.600 1.000 0110011b 1.675 1011110b 2.750
0001001b 0.625 1.000 0110100b 1.700 1011111b 2.775
0001010b 0.650 1.000 0110101b 1.725 1100000b 2.800
0001011b 0.675 1.000 0110110b 1.750 1100001b 2.825
0001100b 0.700 1.000 0110111b 1.775 1100010b 2.850
0001101b 0.725 1.000 0111000b 1.800 1100011b 2.875
0001110b 0.750 1.000 0111001b 1.825 1100100b 2.900
0001111b 0.775 1.000 0111010b 1.850 1100101b 2.925
0010000b 0.800 1.000 0111011b 1.875 1100110b 2.950
0010001b 0.825 1.000 0111100b 1.900 1100111b 2.975
0010010b 0.850 1.000 0111101b 1.925 1101000b 3.000
0010011b 0.875 1.000 0111110b 1.950 1101001b 3.025
0010100b 0.900 1.000 0111111b 1.975 1101010b 3.050
0010101b 0.925 1.000 1000000b 2.000 1101011b 3.075
0010110b 0.950 1.000 1000001b 2.025 1101100b 3.100
0010111b 0.975 1.000 1000010b 2.050 1101101b 3.125
0011000b 1.000 1.000 1000011b 2.075 1101110b 3.150
0011001b 1.025 1.025 1000100b 2.100 1101111b 3.175
0011010b 1.050 1.050 1000101b 2.125 1110000b 3.200
0011011b 1.075 1.075 1000110b 2.150 1110001b 3.225
0011100b 1.100 1.100 1000111b 2.175 1110010b 3.250
0011101b 1.125 1.125 1001000b 2.200 1110011b 3.275
0011110b 1.150 1.150 1001001b 2.225 1110100b 3.300
0011111b 1.175 1.175 1001010b 2.250 1110101b 3.325
0100000b 1.200 1.200 1001011b 2.275 1110110b 3.350
0100001b 1.225 1.225 1001100b 2.300 1110111b 3.375
0100010b 1.250 1.250 1001101b 2.325 1111000b 3.400
0100011b 1.275 1.275 1001110b 2.350 1111001b 3.425
0100100b 1.300 1.300 1001111b 2.375 1111010b 3.450
0100101b 1.325 1.325 1010000b 2.400 1111011b 3.475
0100110b 1.350 1.350 1010001b 2.425 1111100b 3.500
0100111b 1.375 1.375 1010010b 2.450 1111101b 3.525
0101000b 1.400 1.400 1010011b 2.475 1111110b 3.550
0101001b 1.425 1.425 1010100b 2.500 1111111b 3.575
0101010b 1.450 1.450 1010101b 2.525 — —

5.3.1 Controller Overview

The controllers are fast-reacting, high-frequency, scalable output-power controllers capable of driving two external N-MOSFETs. The controllers use the D-CAP2 control scheme that optimizes transient responses at high load currents for such applications as CORE and DDR supplies. The output voltage is compared with and internal reference voltage after divider resistors. The PWM comparator determines the timing to turn on the high-side MOSFET. The PWM comparator response maintains a very small PWM output ripple voltage. Because the device does not have a dedicated oscillator for the on-board control loop, the switching cycle is controlled by the adaptive on-time circuit. The on-time is controlled to meet the target switching frequency by feed-forwarding the input and output voltage into the on-time one-shot timer.

The D-CAP2 control scheme has an injected ripple from the SW node that is added on to the reference voltage to simulate output ripple, which eliminates the need for ESR-induced output ripple from D-CAP mode control. Therefore, low-ESR output capacitors (such as low-cost ceramic MLCC capacitors) can be used with the controllers. Figure 5-2 shows the block diagram for the controller

TPS6508700 870_DCAP2_BlockDiagram.gif Figure 5-2 Controller Block Diagram

5.3.2 Converter Overview

The PMIC synchronous step-down DC-DC converters include a unique, hysteretic PWM-controller scheme which enables a high switching-frequency converter, excellent transient and AC load regulation as well as operation with cost-competitive external components. The controller topology supports forced PWM mode as well as power-save mode operation. Power-save mode operation, or PFM mode, reduces the quiescent current consumption and ensures high conversion efficiency at light loads by skipping switch pulses. In forced PWM mode, the device operates on a quasi-fixed frequency, avoids pulse skipping, and allows filtering of the switch noise by external filter components. The PMIC device offers fixed output voltage options featuring a small solution size by using only three external components per converter.

A significant advantage of a PMIC over other hysteretic PWM controller topologies is the excellent AC load transient regulation capability of PMICs. When the output voltage falls below the threshold of the error comparator, a switch pulse is initiated, and the high-side switch is turned on. The switch remains turned on until a minimum on-time (tONmin) expires and the output voltage trips the threshold of the error comparator, or until the inductor current reaches the current limit of the high-side switch. When the high-side switch turns off, the low-side switch rectifier is turned on and the inductor current ramps down until the high-side switch turns on again or the inductor current reaches zero. In forced PWM mode operation, negative inductor current is allowed to enable continuous conduction mode even at no load condition.

TPS6508700 DCS-Control_BlockDiagram.gif Figure 5-3 Converter Block Diagram

5.3.3 Dynamic Voltage Scaling

The buck regulators (BUCK1 through BUCK6) support dynamic voltage scaling (DVS) for maximum system efficiency. The VR outputs can slew up and slew down in either 10-mV or 25-mV steps using the 7-bit voltage ID (VID) defined in Section 4.7 and Section 4.8. The DVS slew rate is 2.5 mV/µs (minimum). To meet the minimum slew rate, VID progresses to the next code at 3-µs (nominal) interval per 10-mV or at 6-µs interval per 25-mV steps. When DVS is active, the VR is forced into PWM mode, unless the BUCKx_DECAY bit is 1b, to ensure the output keeps track of the VID code with minimal delay. Additionally, the PGOOD bits (in the PG_STATUS1 and PG_STATUS2 registers) are masked when DVS is in progress. Figure 5-4 shows an example of slew down and slew up from one VID to another (step size of 10 mV).

TPS6508700 DVS_td_public_swcs127.gif Figure 5-4 DVS Timing Diagram I (BUCKx_DECAY = 0b)

When DVS is enabled and the BUCKx_VID[6:0] bit is set to any setting except 0b or 1b, the slew rate of the voltage is as shown in Figure 5-4.

As shown in Figure 5-5, if a BUCKx_VID[6:0] bit is set to 0000000b, the output voltage of that buck slews down to 0.5 V first, and then drifts down to 0 V as the SMPS stops switching. Subsequently, if a BUCKx_VID[6:0] bit is set to a value (neither 0000000b nor 0000001b) when the output voltage of that buck is less than 0.5 V, the VR ramps up to 0.5 V first and the soft-start time begins. The output voltage then slews up to the target voltage of the previously mentioned slew rate.

NOTE

A fixed 200 µs of soft-start time is reserved for the output voltage to reach 0.5 V. In this case, however, the SMPS is not forced into PWM mode as it otherwise could cause the output voltage to droop momentarily if the output voltage might have been drifting above 0.5 V for any reason.
TPS6508700 BSW_DVS_TD2_public.gif Figure 5-5 DVS Timing Diagram II (BUCKx_DECAY = 0b)

5.3.4 Current Limit

The buck controllers (BUCK1, BUCK2, and BUCK6) have inductor-valley current-limit architecture and the current limit is programmable by an external resistor at the ILIMx pin. Equation 1 shows the calculation for a desired resistor value, depending on specific application conditions. The ILIMREF current is the current source out of the ILIMx pin that is typically 50 µA, and RDSON is the maximum channel resistance of the low-side FET. The scaling factor is 1.3 to consider all errors and temperature variations of RDSON, ILIMREF, and RILIM. Finally, 8 is another scaling factor associated with the ILIMREF current.

Equation 1. TPS6508700 eq1_swcs127.gif

where

  • ILIM is the target current limit. An appropriate margin must be allowed when determining the value of ILIM from the maximum DC load current of the output.
  • Iripple(min) is the minimum peak-to-peak inductor ripple current for a given output voltage.
Equation 2. TPS6508700 eq2_swcs127.gif

where

  • Lmax is the maximum inductance.
  • fsw(max) is the maximum switching frequency.
  • VIN(MIN) is the minimum input voltage to the external power stage.

The inductor of the buck converter limits the peak current. This current limiting is done on a cycle-by-cycle basis to the current limit (IIND_LIM), which is specified in Section 4.8.

5.4 LDO Regulators and Load Switches

5.4.1 VTT LDO

Powered from the BUCK6 output, the VTT LDO tracks the VBUCK6 voltage by regulating its output to a half of its input. The LDO current limit is OTP dependent, and it is designed specifically to power DDR memory. The LDO core is a transconductance amplifier with large gain, and it drives a current output stage that either sources or sinks current depending on the deviation of VTTFB pin voltage from the target regulation voltage.

5.4.2 LDOA1–LDOA3

The TPS6508700 device integrates three general-purpose LDOs. LDOA1 is powered from a 5-V supply through the DRV5V_2_A1 pin and it can be factory configured as an always-on rail as long as a valid power supply is available at the VSYS pin. For LDOA1 output voltage options, see Table 5-4. LDOA2 and LDOA3 share a power input pin (PVINLDOA2_A3). The output regulation voltages are set by writing to the LDOAx_VID[3:0] bits (registers 0x9A, 0x9B, and 0xAE). For LDOA2 and LDOA3 output voltage options, See Table 5-5.

Table 5-4 LDOA1 Output Voltage Options

VID Bits VOUT VID Bits VOUT VID Bits VOUT VID Bits VOUT
0000b 1.35 0100b 1.8 1000b 2.3 1100b 2.85
0001b 1.5 0101b 1.9 1001b 2.4 1101b 3.0
0010b 1.6 0110b 2.0 1010b 2.5 1110b 3.3
0011b 1.7 0111b 2.1 1011b 2.6 1111b Not Used

Table 5-5 LDOA2 and LDOA3 Output Voltage Options

VID Bits VOUT VID Bits VOUT VID Bits VOUT VID Bits VOUT
0000b 0.70 0100b 0.90 1000b 1.10 1100b 1.30
0001b 0.75 0101b 0.95 1001b 1.15 1101b 1.35
0010b 0.80 0110b 1.00 1010b 1.20 1110b 1.40
0011b 0.85 0111b 1.05 1011b 1.25 1111b 1.50

5.4.3 Load Switches

The PMIC features three general-purpose load switches. The SWA1 switch has a dedicated power input pin (PVINSWA1). The SWB1 and SWB2 pins share one power input pin (PVINSWB1_B2). All switches have built-in slew-rate control during startup to limit the inrush current.

5.5 Power Good Information (PGOOD or PG) and GPO Pins

The device provides information on status of VRs through four GPO pins along with the power-good status registers defined in Section 5.9.47 and Section 5.9.48. Power good information of any individual VR and load switch can be assigned to be part of the PGOOD tree as defined from Section 5.9.37 to Section 5.9.44. PGOOD assertion delays are programmable from 0 ms to 15 ms for GPO1, 0 ms to 100 ms for GPO2 and GPO4, and 2.5 ms to 100 ms for GPO3 as defined in Section 5.9.19 and Section 5.9.31 (respectively).

TPS6508700 PowerGoodTree.gif Figure 5-6 Power Good Tree

Alternatively, the GPOs can be used as general-purpose outputs controlled by the user through I2C. For more information on controlling the GPOs in I2C control mode, see Section 5.9.34.

5.6 Power Sequencing and Voltage-Rail Control

When a valid power source is available at the VSYS pin (VSYS ≥ 5.6 V), the internal analog blocks, including LDO5 and LDO3P3, are enabled. The device then has three ways of sequencing the rails during power up and power down:

  • Rail enabled by CTLx pin
  • Rail enabled by power good, (PG) of the previously enabled rail
  • Rail enabled by I2C software command

5.6.1 Power-Up and Power-Down Sequencing

The power-up and power-down sequence uses the CTL1, CTL4, and CTL5 pins to enable and disable regulators as required by the system. Figure 5-7 shows the sequencing of these enables in a typical power-up and power-down sequence.

TPS6508700 8700_Timing_G3_S0.gif
1. CTLx are control signals from the discrete digital from the processor to enable the rails.
2. The power fault is masked for 10 ms when the regulator is enabled.
Figure 5-7 Power-Up and Power-Down Sequence

Table 5-6 lists the system power states.

Table 5-6 System Power States

STATE GPIO_G3 EN_S5 CTL4 CTL5
G3’ 1 0 1 0
G3’ 1 1 1 0
G3 state 0 0 0 0
S5 state 0 1 1 1

5.6.2 Emergency Shutdown

Figure 5-8 shows the emergency shutdown sequence.

TPS6508700 CAT_Emergency_Shutdown.gif Figure 5-8 Emergency Shutdown Sequence

When the VSYS voltage crosses below VSYS_UVLO_5V, all power good pins are deasserted, and after 444 ns (nominal) of delay, all VRs shut down. Upon shutdown, all internal discharge resistors are set to 100 Ω to ensure timely decay of all VR outputs. Other conditions that cause emergency shutdown are the die temperature rising above the critical temperature threshold (TCRIT), and deassertion of the power good of any rail (configurable).

5.7 Device Functional Modes

5.7.1 Off Mode

When the power supply at the VSYS pin is less than VSYS_UVLO_5V (5.4-V nominal) + VSYS_UVLO_5V_HYS (0.2-V nominal), the device is in off mode, where all output rails are disabled. If the supply voltage is greater than VSYS_UVLO_3V (3.6-V nominal) + VSYS_UVLO_3V_HYS (0.15-V nominal) while the supply voltage is still less than VSYS_UVLO_5V + VSYS_UVLO_5V_HYS, then the internal band-gap reference (VREF pin) along with LDO3P3 are enabled and regulated at target values.

5.7.2 Standby Mode

When the power supply at the VSYS pin rises above VSYS_UVLO_5V + VSYS_UVLO_5V_HYS, the device enters standby mode, where all internal reference and regulators (LDO3P3 and LDO5) are up and running, and I2C interface and CTL pins are ready to respond. All default registers defined in Section 5.9.1 should have been loaded from one-time programmable (OTP) memory by now. Quiescent current consumption in standby mode is specified in Section 4.5.

5.7.3 Active Mode

The device proceeds to active mode when any output rail is enabled through an input pin as discussed in Section 5.6 or by writing to EN bits through I2C. The output regulation voltage can also be changed by writing to the VID bits defined in Section 5.9.1.

5.8 I2C Interface

The I2C interface is a 2-wire serial interface. The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, DATA, and CLK. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives data, transmits data, or both on the bus under control of the master device.

The TPS6508700 device works as a slave and supports the following data transfer modes, as defined in the I2C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode
(1 Mbps). The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents are loaded when the VSYS voltage is higher than VSYS_UVLO_5V and is applied to the TPS6508700 device. The I2C interface is running from an internal oscillator that is automatically enabled when access to the interface is avaialble.

The data transfer protocol for fast and standard modes are exactly the same, therefore, they are referred to as F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as H/S-mode.

The TPS6508700 device supports 7-bit addressing; however, 10-bit addressing and a general call address are not supported. The default device address is 0x5E.

5.8.1 F/S-Mode Protocol

The master initiates a data transfer by generating a start condition. The start condition is a high-to-low transition that occurs on the SDA line while SCL is high (see Figure 5-9). All I2C-compatible devices should recognize a start condition.

The master then generates the SCL pulses, and transmits the 7-bit address and the read-write direction bit, R/W, on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see
Figure 5-10). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 5-11) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master identifies that the communication link with a slave has been established.

The master generates additional SCL cycles to either transmit data to the slave (R/W bit is 0b) or receive data from the slave (R/W bit is 1b). In either case, the receiver must acknowledge the data sent by the transmitter. An acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as required.

To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 5-9). This process releases the bus and stops the communication link with the addressed slave. All I2C-compatible devices must recognize the stop condition. Upon receiving a stop condition, all devices identify that the bus is released, and wait for a start condition followed by a matching address.

TPS6508700 start_stop_conditions_swcs127.gif Figure 5-9 START and STOP Conditions
TPS6508700 bit_transfer_swcs127.gif Figure 5-10 Bit Transfer on the I2C Bus
TPS6508700 acknowledge_i2c_bus_swcs127.gif Figure 5-11 Acknowledge on the I2C Bus
TPS6508700 I2c_bus_protocol_swcs127.gif Figure 5-12 I2C Bus Protocol
TPS6508700 I2C_interface_write_swcs127.gif Figure 5-13 I2C Interface WRITE to TPS6508700 in F/S Mode
TPS6508700 I2C_interface_read_swcs127.gif Figure 5-14 I2C Interface READ From TPS6508700 in F/S Mode
(Only Repeated START is Supported)

5.9 Register Maps

5.9.1 Register Map Summary

Table 5-7 lists the memory-mapped registers for the TPS6508700. All register offset addresses not listed in Table 5-7 should be considered as reserved locations and the register contents should not be modified.

Table 5-7 Register Map Summary

Offset Acronym Short Description Section
1h DEVICEID Device ID code indicating revision Go
2h IRQ Interrupt statuses Go
3h IRQ_MASK Interrupt masking Go
4h PMICSTAT PMIC temperature indicator Go
5h SHUTDNSRC Shutdown root cause indicator bits Go
21h BUCK2CTRL BUCK2 decay control and voltage select Go
22h BUCK3DECAY BUCK3 decay control Go
23h BUCK3VID BUCK3 voltage select Go
24h BUCK3SLPCTRL BUCK3 voltage select for SLEEP state Go
25h BUCK4CTRL BUCK4 control Go
26h BUCK5CTRL BUCK5 control Go
27h BUCK6CTRL BUCK6 control Go
28h LDOA2CTRL LDOA2 control Go
29h LDOA3CTRL LDOA3 control Go
40h DISCHCTRL1 Discharge resistors for each rail control Go
41h DISCHCTRL2 Discharge resistors for each rail control Go
42h DISCHCTRL3 Discharge resistors for each rail control Go
43h PG_DELAY1 System Power Good on GPO3 (if GPO3 is programmed to be system PG) Go
91h FORCESHUTDN Software force shutdown Go
93h BUCK2SLPCTRL BUCK2 voltage select for SLEEP state Go
94h BUCK4VID BUCK4 voltage select Go
95h BUCK4SLPVID BUCK4 voltage select for SLEEP state Go
96h BUCK5VID BUCK5 voltage select Go
97h BUCK5SLPVID BUCK5 voltage select for SLEEP state Go
98h BUCK6VID BUCK6 voltage select Go
99h BUCK6SLPVID BUCK6 voltage select for SLEEP state Go
9Ah LDOA2VID LDOA2 voltage select Go
9Bh LDOA3VID LDOA3 voltage select Go
9Ch BUCK123CTRL BUCK1, 2, and 3 disable and PFM/PWM mode control Go
9Dh PG_DELAY2 System Power Good on GPO1, 2, and 4 (if GPOs are programmed to be system PG) Go
9Fh SWVTT_DIS SWs and VTT I2C disable bits Go
A0h I2C_RAIL_EN1 I2C enable control of individual rails Go
A1h I2C_RAIL_EN2/GPOCTRL I2C enable control of individual rails and I2C controlled GPOs, high or low Go
A2h PWR_FAULT_MASK1 Power fault masking for individual rails Go
A3h PWR_FAULT_MASK2 Power fault masking for individual rails Go
A4h GPO1PG_CTRL1 Power good tree control for GPO1 Go
A5h GPO1PG_CTRL2 Power good tree control for GPO1 Go
A6h GPO4PG_CTRL1 Power good tree control for GPO4 Go
A7h GPO4PG_CTRL2 Power good tree control for GPO4 Go
A8h GPO2PG_CTRL1 Power good tree control for GPO2 Go
A9h GPO2PG_CTRL2 Power good tree control for GPO2 Go
AAh GPO3PG_CTRL1 Power good tree control for GPO3 Go
ABh GPO3PG_CTRL2 Power good tree control for GPO3 Go
ACh MISCSYSPG Power Good tree control with CTL3 and CTL6 for GPO Go
AEh LDOA1CTRL LDOA1 control for discharge, voltage selection, and enable Go
B0h PG_STATUS1 Power Good statuses for individual rails Go
B1h PG_STATUS2 Power Good statuses for individual rails Go
B2h PWR_FAULT_STATUS1 Power fault statuses for individual rails Go
B3h PWR_FAULT_STATUS2 Power fault statuses for individual rails Go
B4h TEMPCRIT Critical temperature indicators Go
B5h TEMPHOT Hot temperature indicators Go
B6h OC_STATUS Overcurrent fault status Go

Complex bit access types are encoded to fit into small table cells. Table 5-8 shows the codes that are used for access types in this section.

Table 5-8 Access Type Codes

Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-nh Value after reset or the default value

5.9.2 DEVICEID: PMIC Device and Revision ID Register (offset = 1h) [reset = 10h]

DEVICEID is shown in Figure 5-15 and described in Table 5-9.

Return to Summary Table.

Figure 5-15 DEVICEID Register
7 6 5 4 3 2 1 0
REVID[1:0] OTP_VERSION[1:0] PART_NUMBER[3:0]
R-0h R-1h R-0h

Table 5-9 DEVICEID Field Descriptions

Bit Field Type Reset Description
7-6 REVID[1:0] R 0h

Silicon revision ID
5-4 OTP_VERSION[1:0] R 1h

OTP variation ID

0h = A

1h = B

2h = C

3h = D
3-0 PART_NUMBER[3:0] R 0h

Device part number ID

0h = TPS6508700

1h = TPS6508701

Fh = TPS650870F

5.9.3 IRQ: PMIC Interrupt Register (offset = 2h) [reset = 0h]

IRQ is shown in Figure 5-16 and described in Table 5-10.

Return to Summary Table.

Figure 5-16 IRQ Register
7 6 5 4 3 2 1 0
FAULT RESERVED SHUTDN RESERVED DIETEMP
R/W-0h R-0h R/W-0h R-0h R/W-0h

Table 5-10 IRQ Field Descriptions

Bit Field Type Reset Description
7 FAULT R/W 0h

Fault interrupt. Asserted when either condition occurs: SYS < UVLO, power fault of any rail, or die temperature crosses over the critical temperature threshold (TCRIT). The user can read registers 0xB2 through 0xB6 to determine what has caused the interrupt.

0h = Not asserted

1h = Asserted. Host to write 1 to clear.
6-4 RESERVED R 0h
3 SHUTDN R/W 0h

Asserted when PMIC shuts down. To clear indicator, SHUTDNSRC must be cleared first, see Section 5.9.6

0h = Not asserted.

1h = Asserted. Host to write 1 to clear.
2-1 RESERVED R 0h
0 DIETEMP R/W 0h

Die temp interrupt. Asserted when PMIC die temperature crosses above the hot temperature threshold (THOT).

0h = Not asserted.

1h = Asserted. Host to write 1 to clear.

5.9.4 IRQ_MASK: PMIC Interrupt Mask Register (offset = 3h) [reset = FFh]

IRQ_MASK is shown in Figure 5-17 and described in Table 5-11.

Return to Summary Table.

Figure 5-17 IRQ_MASK Register
7 6 5 4 3 2 1 0
MFAULT RESERVED MSHUTDN RESERVED MDIETEMP
R/W-1h R-7h R/W-1h R-3h R/W-1h

Table 5-11 IRQ_MASK Field Descriptions

Bit Field Type Reset Description
7 MFAULT R/W 1h

FAULT interrupt mask.

0h = Not masked.

1h = Masked.
6-4 RESERVED R 7h
3 MSHUTDN R/W 1h

PMIC shutdown event interrupt mask

0h = Not masked.

1h = Masked.
2-1 RESERVED R 3h
0 MDIETEMP R/W 1h

Die temp interrupt mask.

0h = Not masked.

1h = Masked.

5.9.5 PMICSTAT: PMIC Status Register (offset = 4h) [reset = 0h]

PMICSTAT is shown in Figure 5-18 and described in Table 5-12.

Return to Summary Table.

Figure 5-18 PMICSTAT Register
7 6 5 4 3 2 1 0
RESERVED SDIETEMP
R-0h R-0h

Table 5-12 PMICSTAT Field Descriptions

Bit Field Type Reset Description
7-1 RESERVED R 0h
0 SDIETEMP R 0h

PMIC die temperature status.

0h = PMIC die temperature is below THOT.

1h = PMIC die temperature is above THOT.

5.9.6 SHUTDNSRC: PMIC Shut-Down Event Register (offset = 5h) [reset = 0h]

SHUTDNSRC is shown in Figure 5-19 and described in Table 5-13.

Return to Summary Table.

Figure 5-19 SHUTDNSRC Register
7 6 5 4 3 2 1 0
RESERVED COLDOFF UVLO PWRFLT CRITTEMP
R-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 5-13 SHUTDNSRC Field Descriptions

Bit Field Type Reset Description
7-4 RESERVED R 0h
3 COLDOFF R/W 0h

Set by PMIC cleared by host. Host to write 1 to clear. This bit is always 0h for TPS6508700.

0h = Cleared

1h = PMIC was shut down by pulling down CTL1 pin.
2 UVLO R/W 0h

Set by PMIC cleared by host. Host to write 1 to clear.

0h = Cleared

1h = PMIC was shut down due to a UVLO event (VSYS crosses below 5.4 V). Assertion of this bit sets the SHUTDN bit in Section 5.9.3.
1 PWRFLT R/W 0h

Set by PMIC cleared by host. Host to write 1 to clear.

0h = Cleared

1h = PMIC was shut down due to a power fault on a rail with power fault not masked. Assertion of this bit sets the SHUTDN bit in Section 5.9.3.
0 CRITTEMP R/W 0h

Set by PMIC cleared by host. Host to write 1 to clear.

0h = Cleared

1h = PMIC was shut down due to the rise of PMIC die temperature above critical temperature threshold (TCRIT). Assertion of this bit sets the SHUTDN bit in Section 5.9.3.

5.9.7 BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = 50h]

BUCK2CTRL is shown in Figure 5-20 and described in Table 5-14.

Return to Summary Table.

Figure 5-20 BUCK2CTRL Register
7 6 5 4 3 2 1 0
BUCK2_VID[6:0] BUCK2_DECAY
R/W-28h R/W-0h

Table 5-14 BUCK2CTRL Field Descriptions

Bit Field Type Reset Description
7-1 BUCK2_VID[6:0] R/W 28h

This field sets the BUCK2 regulator output regulation voltage in normal mode.
See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges for VOUT options.
0 BUCK2_DECAY R/W 0h

Decay bit

0h = The output slews down to a lower voltage set by the VID bits.

1h = The output decays down to a lower voltage set by the VID bits. Decay rate depends on total capacitance and load present at the output.

5.9.8 BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = 70h]

BUCK3DECAY is shown in Figure 5-21 and described in Table 5-15.

Return to Summary Table.

Figure 5-21 BUCK3DECAY Register
7 6 5 4 3 2 1 0
RESERVED BUCK3_DECAY
R/W-38h R/W-0h

Table 5-15 BUCK3DECAY Field Descriptions

Bit Field Type Reset Description
7-1 RESERVED R/W 38h

Reserved bits are don't care bits, can be 1h or 0h.

0 BUCK3_DECAY R/W 0h

Decay bit

0h = The output slews down to a lower voltage set by the VID bits.

1h = The output decays down to a lower voltage set by the VID bits. Decay rate depends on total capacitance and load present at the output.

5.9.9 BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = 70h]

BUCK3VID is shown in Figure 5-22 and described in Table 5-16.

Return to Summary Table.

Figure 5-22 BUCK3VID Register
7 6 5 4 3 2 1 0
BUCK3_VID[6:0] RESERVED
R/W-38h R/W-0h

Table 5-16 BUCK3VID Field Descriptions

Bit Field Type Reset Description
7-1 BUCK3_VID[6:0] R/W 38h

This field sets the BUCK3 regulator output regulation voltage in normal mode.
See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges for VOUT options.
0 RESERVED R/W 0h

5.9.10 BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = 70h]

BUCK3SLPCTRL is shown in Figure 5-23 and described in Table 5-17.

Return to Summary Table.

Figure 5-23 BUCK3SLPCTRL Register
7 6 5 4 3 2 1 0
BUCK3_SLP_VID[6:0] BUCK3_SLP_EN
R/W-38h R/W-0h

Table 5-17 BUCK3SLPCTRL Field Descriptions

Bit Field Type Reset Description
7-1 BUCK3_SLP_VID[6:0] R/W 38h

This field sets the BUCK3 regulator output regulation voltage in sleep mode. BUCK3_SLP_VID bits are copied to BUCK3_VID bits upon enters sleep mode.
See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges for VOUT options.
0 BUCK3_SLP_EN R/W 0h

BUCK3 sleep mode enable. BUCK3 is factory configured to change to sleep mode voltage either by CTL3/SLPENB1 pin or by CTL6/SLPENB2 pin.

0h = Disable.

1h = Enable.

5.9.11 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = Dh]

BUCK4CTRL is shown in Figure 5-24 and described in Table 5-18.

Return to Summary Table.

Figure 5-24 BUCK4CTRL Register
7 6 5 4 3 2 1 0
RESERVED BUCK4_SLP_EN[1:0] RESERVED BUCK4_MODE BUCK4_DIS
R-0h R/W-0h R/W-3h R/W-0h R/W-1h

Table 5-18 BUCK4CTRL Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R 0h
5-4 BUCK4_SLP_EN[1:0] R/W 0h

BUCK4 sleep mode enable. BUCK4 is factory configured to change to sleep mode voltage either by CTL3/SLPENB1 pin or by CTL6/SLPENB2 pin.

0h = Disable.

1h = Enable.

2h = Enable.

3h = Enable.
3-2 RESERVED R/W 3h

Reserved as 3h. 0h, 1h, and 2h will result in BUCK4 regulation ignoring BUCK4_VID and BUCK4_SLP_VID values.
1 BUCK4_MODE R/W 0h

This field sets the BUCK4 regulator operating mode.

0h = Automatic mode

1h = Forced PWM mode
0 BUCK4_DIS R/W 1h

BUCK4 disable bit. Writing 0 to this bit forces BUCK4 to turn off regardless of any control input pin (CTL1–CTL6) status.

0h = Disable

1h = Enable

5.9.12 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = Dh]

BUCK5CTRL is shown in Figure 5-25 and described in Table 5-19.

Return to Summary Table.

Figure 5-25 BUCK5CTRL Register
7 6 5 4 3 2 1 0
RESERVED BUCK5_SLP_EN[1:0] RESERVED BUCK5_MODE BUCK5_DIS
R-0h R/W-0h R/W-3h R/W-0h R/W-1h

Table 5-19 BUCK5CTRL Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R 0h
5-4 BUCK5_SLP_EN[1:0] R/W 0h

BUCK5 sleep mode enable. BUCK5 is factory configured to change to sleep mode voltage either by CTL3/SLPENB1 pin or by CTL6/SLPENB2 pin.

0h = Disable.

1h = Enable.

2h = Enable.

3h = Enable.
3-2 RESERVED R/W 3h

Reserved as 3h. 0h, 1h, and 2h will result in BUCK5 regulation ignoring BUCK5_VID and BUCK5_SLP_VID values.
1 BUCK5_MODE R/W 0h

This field sets the BUCK5 regulator operating mode.

0h = Automatic mode

1h = Forced PWM mode
0 BUCK5_DIS R/W 1h

BUCK5 disable bit. Writing 0 to this bit forces BUCK5 to turn off regardless of any control input pin (CTL1–CTL6) status.

0h = Disable.

1h = Enable.

5.9.13 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = Dh]

BUCK6CTRL is shown in Figure 5-26 and described in Table 5-20.

Return to Summary Table.

Figure 5-26 BUCK6CTRL Register
7 6 5 4 3 2 1 0
RESERVED BUCK6_SLP_EN[1:0] RESERVED BUCK6_MODE BUCK6_DIS
R-0h R/W-0h R/W-3h R/W-0h R/W-1h

Table 5-20 BUCK6CTRL Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R 0h
5-4 BUCK6_SLP_EN[1:0] R/W 0h

BUCK6 sleep mode enable. BUCK6 is factory configured to change to sleep mode voltage either by CTL3/SLPENB1 pin or by CTL6/SLPENB2 pin.

0h = Disable.

1h = Enable.

2h = Enable.

3h = Enable.
3-2 RESERVED R/W 3h

Reserved as 3h. 0h, 1h, and 2h will result in BUCK6 regulation ignoring BUCK6_VID and BUCK6_SLP_VID values.
1 BUCK6_MODE R/W 0h

This field sets the BUCK6 regulator operating mode.

0h = Automatic mode

1h = Forced PWM mode
0 BUCK6_DIS R/W 1h

BUCK6 disable bit. Writing 0 to this bit forces BUCK6 to turn off regardless of any control input pin (CTL1–CTL6) status.

0h = Disable.

1h = Enable.

5.9.14 LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = Ch]

LDOA2CTRL is shown in Figure 5-27 and described in Table 5-21.

Return to Summary Table.

Figure 5-27 LDOA2CTRL Register
7 6 5 4 3 2 1 0
RESERVED LDOA2_SLP_EN[1:0] RESERVED LDOA2_DIS
R-0h R/W-0h R/W-6h R/W-0h

Table 5-21 LDOA2CTRL Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R 0h
5-4 LDOA2_SLP_EN[1:0] R/W 0h

LDOA2 sleep mode enable. LDOA2 is factory configured to change to sleep mode voltage either by CTL3/SLPENB1 pin or by CTL6/SLPENB2 pin.

0h = Disable.

1h = Enable.

2h = Enable.

3h = Enable.
3-1 RESERVED R/W 6h

Reserved as 3h. 0h, 1h, and 2h will result in LDOA2 regulation ignoring LDOA2_VID and LDOA2_SLP_VID values.
0 LDOA2_DIS R/W 0h

LDOA2 disable bit. Writing 0 to this bit forces LDOA2 to turn off regardless of any control input pin (CTL1–CTL6) status.

0h = Disable.

1h = Enable.

5.9.15 LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = 3Ch]

LDOA3CTRL is shown in Figure 5-28 and described in Table 5-22.

Return to Summary Table.

Figure 5-28 LDOA3CTRL Register
7 6 5 4 3 2 1 0
RESERVED LDOA3_SLP_EN[1:0] RESERVED LDOA3_DIS
R-0h R/W-3h R/W-6h R/W-0h

Table 5-22 LDOA3CTRL Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R 0h
5-4 LDOA3_SLP_EN[1:0] R/W 3h

LDOA3 sleep mode enable. LDOA3 is factory configured to change to sleep mode voltage either by CTL3/SLPENB1 pin or by CTL6/SLPENB2 pin.

0h = Disable.

1h = Enable.

2h = Enable.

3h = Enable.
3-1 RESERVED R/W 6h

Reserved as 3h. 0h, 1h, and 2h will result in LDOA3 regulation ignoring LDOA3_VID and LDOA3_SLP_VID values.
0 LDOA3_DIS R/W 0h

LDOA3 disable bit. Writing 0h to this bit forces LDOA3 to turn off regardless of any control input pin (CTL1–CTL6) status.

0h = Disable

1h = Enable

5.9.16 DISCHCTRL1: Discharge Control1 Register (offset = 40h) [reset = 55h]

DISCHCTRL1 is shown in Figure 5-29 and described in Table 5-23.

Return to Summary Table.

All xx_DISCHG[1:0] bits internally set to 0h whenever the corresponding VR is enabled.

Figure 5-29 DISCHCTRL1 Register
7 6 5 4 3 2 1 0
BUCK4_DISCHG[1:0] BUCK3_DISCHG[1:0] BUCK2_DISCHG[1:0] BUCK1_DISCHG[1:0]
R/W-1h R/W-1h R/W-1h R/W-1h

Table 5-23 DISCHCTRL1 Field Descriptions

Bit Field Type Reset Description
7-6 BUCK4_DISCHG[1:0] R/W 1h

BUCK4 discharge resistance

0h = no discharge

1h = 100 Ω

2h = 200 Ω

3h = 500 Ω
5-4 BUCK3_DISCHG[1:0] R/W 1h

BUCK3 discharge resistance

0h = no discharge

1h = 100 Ω

2h = 200 Ω

3h = 500 Ω
3-2 BUCK2_DISCHG[1:0] R/W 1h

BUCK2 discharge resistance

0h = no discharge

1h = 100 Ω

2h = 200 Ω

3h = 500 Ω
1-0 BUCK1_DISCHG[1:0] R/W 1h

BUCK1 discharge resistance

0h = no discharge

1h = 100 Ω

2h = 200 Ω

3h = 500 Ω

5.9.17 DISCHCTRL2: Discharge Control2 Register (offset = 41h) [reset = 55h]

DISCHCTRL2 is shown in Figure 5-30 and described in Table 5-24.

Return to Summary Table.

All xx_DISCHG[1:0] bits internally set to 0h whenever the corresponding VR is enabled.

Figure 5-30 DISCHCTRL2 Register
7 6 5 4 3 2 1 0
LDOA2_DISCHG[1:0] SWA1_DISCHG[1:0] BUCK6_DISCHG[1:0] BUCK5_DISCHG[1:0]
R/W-1h R/W-1h R/W-1h R/W-1h

Table 5-24 DISCHCTRL2 Field Descriptions

Bit Field Type Reset Description
7-6 LDOA2_DISCHG[1:0] R/W 1h

LDOA2 discharge resistance

0h = no discharge

1h = 100 Ω

2h = 200 Ω

3h = 500 Ω
5-4 SWA1_DISCHG[1:0] R/W 1h

SWA1 discharge resistance

0h = no discharge

1h = 100 Ω

2h = 200 Ω

3h = 500 Ω
3-2 BUCK6_DISCHG[1:0] R/W 1h

BUCK6 discharge resistance

0h = no discharge

1h = 100 Ω

2h = 200 Ω

3h = 500 Ω
1-0 BUCK5_DISCHG[1:0] R/W 1h

BUCK5 discharge resistance

0h = no discharge

1h = 100 Ω

2h = 200 Ω

3h = 500 Ω

5.9.18 DISCHCTRL3: Discharge Control3 Register (offset = 42h) [reset = 15h]

DISCHCTRL3 is shown in Figure 5-31 and described in Table 5-25.

Return to Summary Table.

All xx_DISCHG[1:0] bits internally set to 0h whenever the corresponding VR is enabled.

Figure 5-31 DISCHCTRL3 Register
7 6 5 4 3 2 1 0
RESERVED SWB2_DISCHG[1:0] SWB1_DISCHG[1:0] LDOA3_DISCHG[1:0]
R-0h R/W-1h R/W-1h R/W-1h

Table 5-25 DISCHCTRL3 Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R 0h
5-4 SWB2_DISCHG[1:0] R/W 1h

SWB2 discharge resistance

0h = no discharge

1h = 100 Ω

2h = 200 Ω

3h = 500 Ω
3-2 SWB1_DISCHG[1:0] R/W 1h

SWB1 discharge resistance

0h = no discharge

1h = 100 Ω

2h = 200 Ω

3h = 500 Ω
1-0 LDOA3_DISCHG[1:0] R/W 1h

LDOA3 discharge resistance

0h = no discharge

1h = 100 Ω

2h = 200 Ω

3h = 500 Ω

5.9.19 PG_DELAY1: Power Good Delay1 Register (offset = 43h) [reset = 0h]

PG_DELAY1 is shown in Figure 5-32 and described in Table 5-26.

Return to Summary Table.

Programmable power good delay for GPO3 pin, measured from the moment when all VRs assigned to GPO3 pin reach their regulation range to power good assertion. This register is optional as the PMIC can be programmed for system PG, level shifter or I2C controller GPO.

Figure 5-32 PG_DELAY1 Register
7 6 5 4 3 2 1 0
RESERVED GPO3_PG_DELAY[2:0]
R-0h R/W-0h

Table 5-26 PG_DELAY1 Field Descriptions

Bit Field Type Reset Description
7-3 RESERVED R 0h
2-0 GPO3_PG_DELAY[2:0] R/W 0h

Programmable delay power good or level shifter for GPO3 pin. Measured from the moment when all rails grouped to this pin reach their regulation range. All values have ±10% variation.
Register not used (GPO3 controlled by I2C)

0h = 2.5 ms

1h = 5 ms

2h = 10 ms

3h = 15 ms

4h = 20 ms

5h = 50 ms

6h = 75 ms

7h = 100 ms

5.9.20 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0h]

FORCESHUTDN is shown in Figure 5-33 and described in Table 5-27.

Return to Summary Table.

Figure 5-33 FORCESHUTDN Register
7 6 5 4 3 2 1 0
RESERVED SDWN
R-0h R/W-0h

Table 5-27 FORCESHUTDN Field Descriptions

Bit Field Type Reset Description
7-1 RESERVED R 0h
0 SDWN R/W 0h

Forces reset of the PMIC and reset of all registers. The bit is self-clearing.

0h = No action.

1h = PMIC is forced to shut down.

5.9.21 BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = 50h]

BUCK2SLPCTRL is shown in Figure 5-34 and described in Table 5-28.

Return to Summary Table.

Figure 5-34 BUCK2SLPCTRL Register
7 6 5 4 3 2 1 0
BUCK2_SLP_VID[6:0] BUCK2_SLP_EN
R/W-28h R/W-0h

Table 5-28 BUCK2SLPCTRL Field Descriptions

Bit Field Type Reset Description
7-1 BUCK2_SLP_VID[6:0] R/W 28h

This field sets the BUCK2 regulator output regulation voltage in sleep mode. Mapping between bits and output voltage is defined as in Section 5.9.7.
0 BUCK2_SLP_EN R/W 0h

BUCK2 sleep mode enable. BUCK2 is factory configured to change to sleep mode voltage either by CTL3/SLPENB1 pin or by CTL6/SLPENB2 pin.

0h = Disable.

1h = Enable.

5.9.22 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = 20h]

BUCK4VID is shown in Figure 5-35 and described in Table 5-29.

Return to Summary Table.

Figure 5-35 BUCK4VID Register
7 6 5 4 3 2 1 0
BUCK4_VID[6:0] BUCK4_DECAY
R/W-10h R/W-0h

Table 5-29 BUCK4VID Field Descriptions

Bit Field Type Reset Description
7-1 BUCK4_VID[6:0] R/W 10h

This field sets the BUCK4 regulator output regulation voltage in normal mode.
See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges for VOUT options.
0 BUCK4_DECAY R/W 0h

Decay bit

0h = The output slews down to a lower voltage set by the VID bits.

1h = The output decays down to a lower voltage set by the VID bits. Decay rate depends on total capacitance and load present at the output.

5.9.23 BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = 20h]

BUCK4SLPVID is shown in Figure 5-36 and described in Table 5-30.

Return to Summary Table.

Figure 5-36 BUCK4SLPVID Register
7 6 5 4 3 2 1 0
BUCK4_SLP_VID[6:0] RESERVED
R/W-10h R-0h

Table 5-30 BUCK4SLPVID Field Descriptions

Bit Field Type Reset Description
7-1 BUCK4_SLP_VID[6:0] R/W 10h

This field sets the BUCK4 regulator output regulation voltage in sleep mode.
See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges for VOUT options.
0 RESERVED R 0h

5.9.24 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = 70h]

BUCK5VID is shown in Figure 5-37 and described in Table 5-31.

Return to Summary Table.

Figure 5-37 BUCK5VID Register
7 6 5 4 3 2 1 0
BUCK5_VID[6:0] BUCK5_DECAY
R/W-38h R/W-0h

Table 5-31 BUCK5VID Field Descriptions

Bit Field Type Reset Description
7-1 BUCK5_VID[6:0] R/W 38h

This field sets the BUCK5 regulator output regulation voltage in normal mode.
See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges for VOUT options.
0 BUCK5_DECAY R/W 0h

Decay bit

0h = The output slews down to a lower voltage set by the VID bits.

1h = The output decays down to a lower voltage set by the VID bits. Decay rate depends on total capacitance and load present at the output.

5.9.25 BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = E8h]

BUCK5SLPVID is shown in Figure 5-38 and described in Table 5-32.

Return to Summary Table.

Figure 5-38 BUCK5SLPVID Register
7 6 5 4 3 2 1 0
BUCK5_SLP_VID[6:0] RESERVED
R/W-74h R-0h

Table 5-32 BUCK5SLPVID Field Descriptions

Bit Field Type Reset Description
7-1 BUCK5_SLP_VID[6:0] R/W 74h

This field sets the BUCK5 regulator output regulation voltage in sleep mode.
See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges for VOUT options.
0 RESERVED R 0h

5.9.26 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = E8h]

BUCK6VID is shown in Figure 5-39 and described in Table 5-33.

Return to Summary Table.

Figure 5-39 BUCK6VID Register
7 6 5 4 3 2 1 0
BUCK6_VID[6:0] BUCK6_DECAY
R/W-74h R/W-0h

Table 5-33 BUCK6VID Field Descriptions

Bit Field Type Reset Description
7-1 BUCK6_VID[6:0] R/W 74h

This field sets the BUCK6 regulator output regulation voltage in normal mode.
See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges for VOUT options.
0 BUCK6_DECAY R/W 0h

Decay bit

0h = The output slews down to a lower voltage set by the VID bits.

1h = The output decays down to a lower voltage set by the VID bits. Decay rate depends on total capacitance and load present at the output.

5.9.27 BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = E8h]

BUCK6SLPVID is shown in Figure 5-40 and described in Table 5-34.

Return to Summary Table.

Figure 5-40 BUCK6SLPVID Register
7 6 5 4 3 2 1 0
BUCK6_SLP_VID[6:0] RESERVED
R/W-74h R-0h

Table 5-34 BUCK6SLPVID Field Descriptions

Bit Field Type Reset Description
7-1 BUCK6_SLP_VID[6:0] R/W 74h

This field sets the BUCK6 regulator output regulation voltage in normal mode.
See Table 5-2 and Table 5-3 for 10-mV and 25-mV step ranges for VOUT options.
0 RESERVED R 0h

5.9.28 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = FFh]

LDOA2VID is shown in Figure 5-41 and described in Table 5-35.

Return to Summary Table.

Figure 5-41 LDOA2VID Register
7 6 5 4 3 2 1 0
LDOA2_SLP_VID[3:0] LDOA2_VID[3:0]
R/W-Fh R/W-Fh

Table 5-35 LDOA2VID Field Descriptions

Bit Field Type Reset Description
7-4 LDOA2_SLP_VID[3:0] R/W Fh

This field sets the LDOA2 regulator output regulation voltage in sleep mode.
See Table 5-5 for VOUT options.
3-0 LDOA2_VID[3:0] R/W Fh

This field sets the LDOA2 regulator output regulation voltage in normal mode.
See Table 5-5 for VOUT options.

5.9.29 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = AAh]

LDOA3VID is shown in Figure 5-42 and described in Table 5-36.

Return to Summary Table.

Figure 5-42 LDOA3VID Register
7 6 5 4 3 2 1 0
LDOA3_SLP_VID[3:0] LDOA3_VID[3:0]
R/W-Ah R/W-Ah

Table 5-36 LDOA3VID Field Descriptions

Bit Field Type Reset Description
7-4 LDOA3_SLP_VID[3:0] R/W Ah

This field sets the LDOA3 regulator output regulation voltage in sleep mode.
See Table 5-5 for VOUT options.
3-0 LDOA3_VID[3:0] R/W Ah

This field sets the LDOA3 regulator output regulation voltage in normal mode.
See Table 5-5 for VOUT options.

5.9.30 BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = 7h]

BUCK123CTRL is shown in Figure 5-43 and described in Table 5-37.

Return to Summary Table.

Figure 5-43 BUCK123CTRL Register
7 6 5 4 3 2 1 0
SPARE BUCK3_MODE BUCK2_MODE BUCK1_MODE BUCK3_DIS BUCK2_DIS BUCK1_DIS
R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h R/W-1h R/W-1h

Table 5-37 BUCK123CTRL Field Descriptions

Bit Field Type Reset Description
7-6 SPARE R/W 0h

Spare bits.

5 BUCK3_MODE R/W 0h

This field sets the BUCK3 regulator operating mode.

0h = Automatic mode

1h = Forced PWM mode
4 BUCK2_MODE R/W 0h

This field sets the BUCK2 regulator operating mode.

0h = Automatic mode

1h = Forced PWM mode
3 BUCK1_MODE R/W 0h

This field sets the BUCK1 regulator operating mode.

0h = Automatic mode

1h = Forced PWM mode
2 BUCK3_DIS R/W 1h

BUCK3 disable bit. Writing 0 to this bit forces BUCK3 to turn off regardless of any control input pin (CTL1–CTL6) status.

0h = Disable

1h = Enable
1 BUCK2_DIS R/W 1h

BUCK2 disable bit. Writing 0 to this bit forces BUCK2 to turn off regardless of any control input pin (CTL1–CTL6) status.

0h = Disable

1h = Enable
0 BUCK1_DIS R/W 1h

BUCK1 disable bit. Writing 0 to this bit forces BUCK1 to turn off regardless of any control input pin (CTL1–CTL6) status.

0h = Disable

1h = Enable

5.9.31 PG_DELAY2: Power Good Delay2 Register (offset = 9Dh) [reset = 21h]

PG_DELAY2 is shown in Figure 5-44 and described in Table 5-38.

Return to Summary Table.

Programmable Power Good delay for GPO1, GPO2, and GPO4 pins, measured from the moment when all VRs assigned to respective GPO reach their regulation range to Power Good assertion. This is an optional register as the PMIC can be programmed for system PG, level shifter or I2C controller GPO.

Figure 5-44 PG_DELAY2 Register
7 6 5 4 3 2 1 0
GPO2_PG_DELAY[2:0] GPO4_PG_DELAY[2:0] GPO1_PG_DELAY[1:0]
R/W-1h R/W-0h R/W-1h

Table 5-38 PG_DELAY2 Field Descriptions

Bit Field Type Reset Description
7-5 GPO2_PG_DELAY[2:0] R/W 1h

Programmable delay power good or level shifter for GPO2 pin. Measured from the moment when all rails grouped to this pin reach their regulation range. All values have ±10% variation.

0h = 0 ms

1h = 5 ms

2h = 10 ms

3h = 15 ms

4h = 20 ms

5h = 50 ms

6h = 75 ms

7h = 100 ms
4-2 GPO4_PG_DELAY[2:0] R/W 0h

Programmable delay power good or level shifter for GPO4 pin. Measured from the moment when all rails grouped to this pin reach their regulation range. All values have ±10% variation

0h = 0 ms

1h = 5 ms

2h = 10 ms

3h = 15 ms

4h = 20 ms

5h = 50 ms

6h = 75 ms

7h = 100 ms
1-0 GPO1_PG_DELAY[1:0] R/W 1h

Programmable delay power good or level shifter for GPO1 pin. Measured from the moment when all rails grouped to this pin reach their regulation range. All values have ±10% variation

0h = 0 ms

1h = 5 ms

2h = 10 ms

3h = 15 ms

5.9.32 SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = 0h]

SWVTT_DIS is shown in Figure 5-45 and described in Table 5-39.

Return to Summary Table.

Figure 5-45 SWVTT_DIS Register
7 6 5 4 3 2 1 0
SWB2_DIS SWB1_DIS SWA1_DIS VTT_DIS RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 5-39 SWVTT_DIS Field Descriptions

Bit Field Type Reset Description
7 SWB2_DIS R/W 0h

SWB2 disable bit. Writing 0h to this bit forces SWB2 to turn off regardless of any control input pin (CTL1–CTL6) status.

0h = Disable.

1h = Enable.
6 SWB1_DIS R/W 0h

SWB1 disable bit. Writing 0 to this bit forces SWB1 to turn off regardless of any control input pin (CTL1–CTL6) status.

0h = Disable.

1h = Enable.
5 SWA1_DIS R/W 0h

SWA1 disable bit. Writing 0 to this bit forces SWA1 to turn off regardless of any control input pin (CTL1–CTL6) status.

0h = Disable.

1h = Enable.
4 VTT_DIS R/W 0h

VTT Disable Bit. Writing 0 to this bit forces VTT to turn off regardless of any control input pin (CTL1–CTL6) status.

0h = Disable.

1h = Enable.
3-0 Reserved R/W 0h

Reserved, Keep bit set to 0h at all times. Do not write to 1h.

5.9.33 I2C_RAIL_EN1: VR Pin Enable Override1 Register (offset = A0h) [reset = 80h]

I2C_RAIL_EN1 is shown in Figure 5-46 and described in Table 5-40.

Return to Summary Table.

Figure 5-46 I2C_RAIL_EN1 Register
7 6 5 4 3 2 1 0
LDOA2_EN SWA1_EN BUCK6_EN BUCK5_EN BUCK4_EN BUCK3_EN BUCK2_EN BUCK1_EN
R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 5-40 I2C_RAIL_EN1 Field Descriptions

Bit Field Type Reset Description
7 LDOA2_EN R/W 1h

LDOA2 I2C enable

0h = LDOA2 is enabled or disabled by one of the control input pins or internal PG signal.

1h = LDOA2 is forced on unless LDOA2_DIS = 0.
6 SWA1_EN R/W 0h

SWA1 I2C enable

0h = SWA1 is enabled or disabled by one of the control input pins or internal PG signal.

1h = SWA1 is forced on unless SWA1_DIS = 0.
5 BUCK6_EN R/W 0h

BUCK6 I2C enable

0h = BUCK6 is enabled or disabled by one of the control input pins or internal PG signal.

1h = BUCK6 is forced on unless BUCK6_DIS = 0.
4 BUCK5_EN R/W 0h

BUCK5 I2C enable

0h = BUCK5 is enabled or disabled by one of the control input pins or internal PG signal.

1h = BUCK5 is forced on unless BUCK5_DIS = 0.
3 BUCK4_EN R/W 0h

BUCK4 I2C enable

0h = BUCK4 is enabled or disabled by one of the control input pins or internal PG signal.

1h = BUCK4 is forced on unless BUCK4_DIS = 0.
2 BUCK3_EN R/W 0h

BUCK3 I2C enable

0h = BUCK3 is enabled or disabled by one of the control input pins or internal PG signal.

1h = BUCK3 is forced on unless BUCK3_DIS = 0.
1 BUCK2_EN R/W 0h

BUCK2 I2C enable

0h = BUCK2 is enabled or disabled by one of the control input pins or internal PG signal.

1h = BUCK2 is forced on unless BUCK2_DIS = 0.
0 BUCK1_EN R/W 0h

BUCK1 I2C enable

0h = BUCK1 is enabled or disabled by one of the control input pins or internal PG signal.

1h = BUCK1 is forced on unless BUCK1_DIS = 0.

5.9.34 I2C_RAIL_EN2/GPOCTRL: VR Pin Enable Override2/GPO Control Register
(offset = A1h) [reset = 89h]

I2C_RAIL_EN2/GPOCTRL is shown in Figure 5-47 and described in Table 5-41.

Return to Summary Table.

Figure 5-47 I2C_RAIL_EN2/GPOCTRL Register
7 6 5 4 3 2 1 0
GPO4_LVL GPO3_LVL GPO2_LVL GPO1_LVL VTT_EN SWB2_EN SWB1_EN LDOA3_EN
R/W-1h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h R/W-0h R/W-1h

Table 5-41 I2C_RAIL_EN2/GPOCTRL Field Descriptions

Bit Field Type Reset Description
7 GPO4_LVL R/W 1h

The field is to set GPO4 pin output if the pin is factory-configured as an open-drain general-purpose output.

0h = The pin is driven to logic low.

1h = The pin is driven to logic high.
6 GPO3_LVL R/W 0h

The field is to set GPO3 pin output if the pin is factory-configured as either an open-drain or a push-pull general-purpose output.

0h = The pin is driven to logic low.

1h = The pin is driven to logic high.
5 GPO2_LVL R/W 0h

The field is to set GPO2 pin output if the pin is factory-configured as either an open-drain or a push-pull general-purpose output.

0h = The pin is driven to logic low.

1h = The pin is driven to logic high.
4 GPO1_LVL R/W 0h

The field is to set GPO1 pin output if the pin is factory-configured as either an open-drain or a push-pull general-purpose output.

0h = The pin is driven to logic low.

1h = The pin is driven to logic high.
3 VTT_EN R/W 1h

VTT LDO I2C enable

0h = VTT LDO is enabled or disabled by one of the control input pins or internal PG signals.

1h = VTT LDO is forced on unless VTT_DIS = 0.
2 SWB2_EN R/W 0h

SWB2 I2C enable

0h = SWB2 is enabled or disabled by one of the control input pins or internal PG signals.

1h = SWB2 is forced on unless SWB2_DIS = 0.
1 SWB1_EN R/W 0h

SWB1 I2C enable

0h = SWB1 is enabled or disabled by one of the control input pins or internal PG signals.

1h = SWB1 is forced on unless SWB1_DIS = 0.
0 LDOA3_EN R/W 1h

LDOA3 I2C enable

0h = LDOA3 is enabled or disabled by one of the control input pins or internal PG signals.

1h = LDOA3 is forced on unless LDOA3_DIS = 0.

5.9.35 PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = C0h]

PWR_FAULT_MASK1 is shown in Figure 5-48 and described in Table 5-42.

Return to Summary Table.

Figure 5-48 PWR_FAULT_MASK1 Register
7 6 5 4 3 2 1 0
LDOA2_FLTMSK SWA1_FLTMSK BUCK6_FLTMSK BUCK5_FLTMSK BUCK4_FLTMSK BUCK3_FLTMSK BUCK2_FLTMSK BUCK1_FLTMSK
R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 5-42 PWR_FAULT_MASK1 Field Descriptions

Bit Field Type Reset Description
7 LDOA2_FLTMSK R/W 1h

LDOA2 power fault mask. When masked, power fault from LDOA2 does not cause PMIC to shutdown.

0h = Not masked

1h = Masked
6 SWA1_FLTMSK R/W 0h

SWA1 power fault mask. When masked, power fault from SWA1 does not cause PMIC to shutdown.

0h = Not masked

1h = Masked
5 BUCK6_FLTMSK R/W 0h

BUCK6 power fault mask. When masked, power fault from BUCK6 does not cause PMIC to shutdown.

0h = Not masked

1h = Masked
4 BUCK5_FLTMSK R/W 0h

BUCK5 power fault mask. When masked, power fault from BUCK5 does not cause PMIC to shutdown.

0h = Not masked

1h = Masked
3 BUCK4_FLTMSK R/W 0h

BUCK4 power fault mask. When masked, power fault from BUCK4 does not cause PMIC to shutdown.

0h = Not masked

1h = Masked
2 BUCK3_FLTMSK R/W 0h

BUCK3 power fault mask. When masked, power fault from BUCK3 does not cause PMIC to shutdown.

0h = Not masked

1h = Masked
1 BUCK2_FLTMSK R/W 0h

BUCK2 power fault mask. When masked, power fault from BUCK2 does not cause PMIC to shutdown.

0h = Not masked

1h = Masked
0 BUCK1_FLTMSK R/W 0h

BUCK1 power fault mask. When masked, power fault from BUCK1 does not cause PMIC to shutdown.

0h = Not masked

1h = Masked

5.9.36 PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = 3Fh]

PWR_FAULT_MASK2 is shown in Figure 5-49 and described in Table 5-43.

Return to Summary Table.

Figure 5-49 PWR_FAULT_MASK2 Register
7 6 5 4 3 2 1 0
RESERVED LDOA1_FLTMSK VTT_FLTMSK SWB2_FLTMSK SWB1_FLTMSK LDOA3_FLTMSK
R-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

Table 5-43 PWR_FAULT_MASK2 Field Descriptions

Bit Field Type Reset Description
7-5 RESERVED R 1h
4 LDOA1_FLTMSK R/W 1h

LDOA1 power fault mask. When masked, power fault from LDOA1 does not cause PMIC to shutdown.

0h = Not masked

1h = Masked
3 VTT_FLTMSK R/W 1h

VTT LDO Power Fault Mask. When masked, power fault from VTT LDO does not cause PMIC to shutdown.

0h = Not masked

1h = Masked
2 SWB2_FLTMSK R/W 1h

SWB2 power fault mask. When masked, power fault from SWB2 does not cause PMIC to shutdown.

0h = Not masked

1h = Masked
1 SWB1_FLTMSK R/W 1h

SWB1 power fault mask. When masked, power fault from SWB1 does not cause PMIC to shutdown.

0h = Not masked

1h = Masked
0 LDOA3_FLTMSK R/W 1h

LDOA3 power fault mask. When masked, power fault from LDOA3 does not cause PMIC to shutdown.

0h = Not masked

1h = Masked

5.9.37 GPO1PG_CTRL1: GPO1 PG Control1 Register (offset = A4h) [reset = C2h]

GPO1PG_CTRL1 is shown in Figure 5-50 and described in Table 5-44.

Return to Summary Table.

Figure 5-50 GPO1PG_CTRL1 Register
7 6 5 4 3 2 1 0
LDOA2_MSK SWA1_MSK BUCK6_MSK BUCK5_MSK BUCK4_MSK BUCK3_MSK BUCK2_MSK BUCK1_MSK
R/W-1h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h

Table 5-44 GPO1PG_CTRL1 Field Descriptions

Bit Field Type Reset Description
7 LDOA2_MSK R/W 1h

0h = LDOA2 PG is part of power good tree of GPO1 pin.

1h = LDOA2 PG is NOT part of power good tree of GPO1 pin and is ignored.
6 SWA1_MSK R/W 1h

0h = SWA1 PG is part of power good tree of GPO1 pin.

1h = SWA1 PG is NOT part of power good tree of GPO1 pin and is ignored.
5 BUCK6_MSK R/W 0h

0h = BUCK6 PG is part of power good tree of GPO1 pin.

1h = BUCK6 PG is NOT part of power good tree of GPO1 pin and is ignored.
4 BUCK5_MSK R/W 0h

0h = BUCK5 PG is part of power good tree of GPO1 pin.

1h = BUCK5 PG is NOT part of power good tree of GPO1 pin and is ignored.
3 BUCK4_MSK R/W 0h

0h = BUCK4 PG is part of power good tree of GPO1 pin.

1h = BUCK4 PG is NOT part of power good tree of GPO1 pin and is ignored.
2 BUCK3_MSK R/W 0h

0h = BUCK3 PG is part of power good tree of GPO1 pin.

1h = BUCK3 PG is NOT part of power good tree of GPO1 pin and is ignored.
1 BUCK2_MSK R/W 1h

0h = BUCK2 PG is part of power good tree of GPO1 pin.

1h = BUCK2 PG is NOT part of power good tree of GPO1 pin and is ignored.
0 BUCK1_MSK R/W 0h

0h = BUCK1 PG is part of power good tree of GPO1 pin.

1h = BUCK1 PG is NOT part of power good tree of GPO1 pin and is ignored.

5.9.38 GPO1PG_CTRL2: GPO1 PG Control2 Register (offset = A5h) [reset = AFh]

GPO1PG_CTRL2 is shown in Figure 5-51 and described in Table 5-45.

Return to Summary Table.

Figure 5-51 GPO1PG_CTRL2 Register
7 6 5 4 3 2 1 0
CTL5_MSK CTL4_MSK CTL2_MSK CTL1_MSK VTT_MSK SWB2_MSK SWB1_MSK LDOA3_MSK
R/W-1h R/W-0h R/W-1h R/W-0h R/W-1h R/W-1h R/W-1h R/W-1h

Table 5-45 GPO1PG_CTRL2 Field Descriptions

Bit Field Type Reset Description
7 CTL5_MSK R/W 1h

0h = CTL5 pin status is part of power good tree of GPO1 pin.

1h = CTL5 pin status is NOT part of power good tree of GPO1 pin and is ignored.
6 CTL4_MSK R/W 0h

0h = CTL4 pin status is part of power good tree of GPO1 pin.

1h = CTL4 pin status is NOT part of power good tree of GPO1 pin and is ignored.
5 CTL2_MSK R/W 1h

0h = CTL2 pin status is part of power good tree of GPO1 pin.

1h = CTL2 pin status is NOT part of power good tree of GPO1 pin and is ignored.
4 CTL1_MSK R/W 0h

0h = CTL1 pin status is part of power good tree of GPO1 pin.

1h = CTL1 pin status is NOT part of power good tree of GPO1 pin and is ignored.
3 VTT_MSK R/W 1h

0h = VTT LDO PG is part of power good tree of GPO1 pin.

1h = VTT LDO PG is NOT part of power good tree of GPO1 pin and is ignored.
2 SWB2_MSK R/W 1h

0h = SWB2 pin status is part of power good tree of GPO1 pin.

1h = SWB2 pin status is NOT part of power good tree of GPO1 pin and is ignored.
1 SWB1_MSK R/W 1h

0h = SWB1 PG is part of power good tree of GPO1 pin.

1h = SWB1 PG is NOT part of power good tree of GPO1 pin and is ignored.
0 LDOA3_MSK R/W 1h

0h = LDOA3 PG is part of power good tree of GPO1 pin.

1h = LDOA3 PG is NOT part of power good tree of GPO1 pin and is ignored.

5.9.39 GPO4PG_CTRL1: GPO4 PG Control1 Register (offset = A6h) [reset = 0h]

GPO4PG_CTRL1is shown in Figure 5-52 and described in Table 5-46.

Return to Summary Table.

Figure 5-52 GPO4PG_CTRL1 Register
7 6 5 4 3 2 1 0
LDOA2_MSK SWA1_MSK BUCK6_MSK BUCK5_MSK BUCK4_MSK BUCK3_MSK BUCK2_MSK BUCK1_MSK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 5-46 GPO4PG_CTRL1 Field Descriptions

Bit Field Type Reset Description
7 LDOA2_MSK R/W 0h

0h = LDOA2 PG is part of power good tree of GPO4 pin.

1h = LDOA2 PG is NOT part of power good tree of GPO4 pin and is ignored.
6 SWA1_MSK R/W 0h

0h = SWA1 PG is part of power good tree of GPO4 pin.

1h = SWA1 PG is NOT part of power good tree of GPO4 pin and is ignored.
5 BUCK6_MSK R/W 0h

0h = BUCK6 PG is part of power good tree of GPO4 pin.

1h = BUCK6 PG is NOT part of power good tree of GPO4 pin and is ignored.
4 BUCK5_MSK R/W 0h

0h = BUCK5 PG is part of power good tree of GPO4 pin.

1h = BUCK5 PG is NOT part of power good tree of GPO4 pin and is ignored.
3 BUCK4_MSK R/W 0h

0h = BUCK4 PG is part of power good tree of GPO4 pin.

1h = BUCK4 PG is NOT part of power good tree of GPO4 pin and is ignored.
2 BUCK3_MSK R/W 0h

0h = BUCK3 PG is part of power good tree of GPO4 pin.

1h = BUCK3 PG is NOT part of power good tree of GPO4 pin and is ignored.
1 BUCK2_MSK R/W 0h

0h = BUCK2 PG is part of power good tree of GPO4 pin.

1h = BUCK2 PG is NOT part of power good tree of GPO4 pin and is ignored.
0 BUCK1_MSK R/W 0h

0h = BUCK1 PG is part of power good tree of GPO4 pin.

1h = BUCK1 PG is NOT part of power good tree of GPO4 pin and is ignored.

5.9.40 GPO4PG_CTRL2: GPO4 PG Control2 Register (offset = A7h) [reset = 0h]

GPO4PG_CTRL2 is shown in Figure 5-53 and described in Table 5-47.

Return to Summary Table.

Figure 5-53 GPO4PG_CTRL2 Register
7 6 5 4 3 2 1 0
CTL5_MSK CTL4_MSK CTL2_MSK CTL1_MSK VTT_MSK SWB2_MSK SWB1_MSK LDOA3_MSK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 5-47 GPO4PG_CTRL2 Field Descriptions

Bit Field Type Reset Description
7 CTL5_MSK R/W 0h

0h = CTL5 pin status is part of power good tree of GPO4 pin.

1h = CTL5 pin status is NOT part of power good tree of GPO4 pin and is ignored.
6 CTL4_MSK R/W 0h

0h = CTL4 pin status is part of power good tree of GPO4 pin.

1h = CTL4 pin status is NOT part of power good tree of GPO4 pin and is ignored.
5 CTL2_MSK R/W 0h

0h = CTL2 pin status is part of power good tree of GPO4 pin.

1h = CTL2 pin status is NOT part of power good tree of GPO4 pin and is ignored.
4 CTL1_MSK R/W 0h

0h = CTL1 pin status is part of power good tree of GPO4 pin.

1h = CTL1 pin status is NOT part of power good tree of GPO4 pin and is ignored.
3 VTT_MSK R/W 0h

0h = VTT LDO PG is part of power good tree of GPO4 pin.

1h = VTT LDO PG is NOT part of power good tree of GPO4 pin and is ignored.
2 SWB2_MSK R/W 0h

0h = SWB2 pin status is part of power good tree of GPO4 pin.

1h = SWB2 pin status is NOT part of power good tree of GPO4 pin and is ignored.
1 SWB1_MSK R/W 0h

0h = SWB1 PG is part of power good tree of GPO4 pin.

1h = SWB1 PG is NOT part of power good tree of GPO4 pin and is ignored.
0 LDOA3_MSK R/W 0h

0h = LDOA3 PG is part of power good tree of GPO4 pin.

1h = LDOA3 PG is NOT part of power good tree of GPO4 pin and is ignored.

5.9.41 GPO2PG_CTRL1: GPO2 PG Control1 Register (offset = A8h) [reset = C0h]

GPO2PG_CTRL1 is shown in Figure 5-54 and described in Table 5-48.

Return to Summary Table.

Figure 5-54 GPO2PG_CTRL1 Register
7 6 5 4 3 2 1 0
LDOA2_MSK SWA1_MSK BUCK6_MSK BUCK5_MSK BUCK4_MSK BUCK3_MSK BUCK2_MSK BUCK1_MSK
R/W-1h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 5-48 GPO2PG_CTRL1 Field Descriptions

Bit Field Type Reset Description
7 LDOA2_MSK R/W 1h

0h = LDOA2 PG is part of power good tree of GPO2 pin.

1h = LDOA2 PG is NOT part of power good tree of GPO2 pin and is ignored.
6 SWA1_MSK R/W 1h

0h = SWA1 PG is part of power good tree of GPO2 pin.

1h = SWA1 PG is NOT part of power good tree of GPO2 pin and is ignored.
5 BUCK6_MSK R/W 0h

0h = BUCK6 PG is part of power good tree of GPO2 pin.

1h = BUCK6 PG is NOT part of power good tree of GPO2 pin and is ignored.
4 BUCK5_MSK R/W 0h

0h = BUCK5 PG is part of power good tree of GPO2 pin.

1h = BUCK5 PG is NOT part of power good tree of GPO2 pin and is ignored.
3 BUCK4_MSK R/W 0h

0h = BUCK4 PG is part of power good tree of GPO2 pin.

1h = BUCK4 PG is NOT part of power good tree of GPO2 pin and is ignored.
2 BUCK3_MSK R/W 0h

0h = BUCK3 PG is part of power good tree of GPO2 pin.

1h = BUCK3 PG is NOT part of power good tree of GPO2 pin and is ignored.
1 BUCK2_MSK R/W 0h

0h = BUCK2 PG is part of power good tree of GPO2 pin.

1h = BUCK2 PG is NOT part of power good tree of GPO2 pin and is ignored.
0 BUCK1_MSK R/W 0h

0h = BUCK1 PG is part of power good tree of GPO2 pin.

1h = BUCK1 PG is NOT part of power good tree of GPO2 pin and is ignored.

5.9.42 GPO2PG_CTRL2: GPO2 PG Control2 Register (offset = A9h) [reset = 2Fh]

GPO2PG_CTRL2 is shown in Figure 5-55 and described in Table 5-49.

Return to Summary Table.

Figure 5-55 GPO2PG_CTRL2 Register
7 6 5 4 3 2 1 0
CTL5_MSK CTL4_MSK CTL2_MSK CTL1_MSK VTT_MSK SWB2_MSK SWB1_MSK LDOA3_ MSK
R/W-0h R/W-0h R/W-1h R/W-0h R/W-1h R/W-1h R/W-1h R/W-1h

Table 5-49 GPO2PG_CTRL2 Field Descriptions

Bit Field Type Reset Description
7 CTL5_MSK R/W 0h

0h = CTL5 pin status is part of power good tree of GPO2 pin.

1h = CTL5 pin status is NOT part of power good tree of GPO2 pin and is ignored.
6 CTL4_MSK R/W 0h

0h = CTL4 pin status is part of power good tree of GPO2 pin.

1h = CTL4 pin status is NOT part of power good tree of GPO2 pin and is ignored.
5 CTL2_MSK R/W 1h

0h = CTL2 pin status is part of power good tree of GPO2 pin.

1h = CTL2 pin status is NOT part of power good tree of GPO2 pin and is ignored.
4 CTL1_MSK R/W 0h

0h = CTL1 pin status is part of power good tree of GPO2 pin.

1h = CTL1 pin status is NOT part of power good tree of GPO2 pin and is ignored.
3 VTT_MSK R/W 1h

0h = VTT LDO PG is part of power good tree of GPO2 pin.

1h = VTT LDO PG is NOT part of power good tree of GPO2 pin and is ignored.
2 SWB2_MSK R/W 1h

0h = SWB2 pin status is part of power good tree of GPO2 pin.

1h = SWB2 pin status is NOT part of power good tree of GPO2 pin and is ignored.
1 SWB1_MSK R/W 1h

0h = SWB1 PG is part of power good tree of GPO2 pin.

1h = SWB1 PG is NOT part of power good tree of GPO2 pin and is ignored.
0 LDOA3_MSK R/W 1h

0h = LDOA3 PG is part of power good tree of GPO2 pin.

1h = LDOA3 PG is NOT part of power good tree of GPO2 pin and is ignored.

5.9.43 GPO3PG_CTRL1: GPO3 PG Control1 Register (offset = AAh) [reset = 0h]

GPO3PG_CTRL1 is shown in Figure 5-56 and described in Table 5-50.

Return to Summary Table.

Figure 5-56 GPO3PG_CTRL1 Register
7 6 5 4 3 2 1 0
LDOA2_MSK SWA1_MSK BUCK6_MSK BUCK5_MSK BUCK4_MSK BUCK3_MSK BUCK2_MSK BUCK1_MSK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 5-50 GPO3PG_CTRL1 Field Descriptions

Bit Field Type Reset Description
7 LDOA2_MSK R/W 0h

0h = LDOA2 PG is part of power good tree of GPO3 pin.

1h = LDOA2 PG is NOT part of power good tree of GPO3 pin and is ignored.
6 SWA1_MSK R/W 0h

0h = SWA1 PG is part of power good tree of GPO3 pin.

1h = SWA1 PG is NOT part of power good tree of GPO3 pin and is ignored.
5 BUCK6_MSK R/W 0h

0h = BUCK6 PG is part of power good tree of GPO3 pin.

1h = BUCK6 PG is NOT part of power good tree of GPO3 pin and is ignored.
4 BUCK5_MSK R/W 0h

0h = BUCK5 PG is part of power good tree of GPO3 pin.

1h = BUCK5 PG is NOT part of power good tree of GPO3 pin and is ignored.
3 BUCK4_MSK R/W 0h

0h = BUCK4 PG is part of power good tree of GPO3 pin.

1h = BUCK4 PG is NOT part of power good tree of GPO3 pin and is ignored.
2 BUCK3_MSK R/W 0h

0h = BUCK3 PG is part of power good tree of GPO3 pin.

1h = BUCK3 PG is NOT part of power good tree of GPO3 pin and is ignored.
1 BUCK2_MSK R/W 0h

0h = BUCK2 PG is part of power good tree of GPO3 pin.

1h = BUCK2 PG is NOT part of power good tree of GPO3 pin and is ignored.
0 BUCK1_MSK R/W 0h

0h = BUCK1 PG is part of power good tree of GPO3 pin.

1h = BUCK1 PG is NOT part of power good tree of GPO3 pin and is ignored.

5.9.44 GPO3PG_CTRL2: GPO3 PG Control2 Register (offset = ABh) [reset = 0h]

GPO3PG_CTRL2 is shown in Figure 5-57 and described in Table 5-51.

Return to Summary Table.

Figure 5-57 GPO3PG_CTRL2 Register
7 6 5 4 3 2 1 0
CTL5_MSK CTL4_MSK CTL2_MSK CTL1_MSK VTT_MSK SWB2_MSK SWB1_MSK LDOA3_MSK
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 5-51 GPO3PG_CTRL2 Field Descriptions

Bit Field Type Reset Description
7 CTL5_MSK R/W 0h

0h = CTL5 pin status is part of power good tree of GPO3 pin.

1h = CTL5 pin status is NOT part of power good tree of GPO3 pin and is ignored.
6 CTL4_MSK R/W 0h

0h = CTL4 pin status is part of power good tree of GPO3 pin.

1h = CTL4 pin status is NOT part of power good tree of GPO3 pin and is ignored.
5 CTL2_MSK R/W 0h

0h = CTL2 pin status is part of power good tree of GPO3 pin.

1h = CTL2 pin status is NOT part of power good tree of GPO3 pin and is ignored.
4 CTL1_MSK R/W 0h

0h = CTL1 pin status is part of power good tree of GPO3 pin.

1h = CTL1 pin status is NOT part of power good tree of GPO3 pin and is ignored.
3 VTT_MSK R/W 0h

0h = VTT LDO PG is part of power good tree of GPO3 pin.

1h = VTT LDO PG is NOT part of power good tree of GPO3 pin and is ignored.
2 SWB2_MSK R/W 0h

0h = SWB2 pin status is part of power good tree of GPO3 pin.

1h = SWB2 pin status is NOT part of power good tree of GPO3 pin and is ignored.
1 SWB1_MSK R/W 0h

0h = SWB1 PG is part of power good tree of GPO3 pin.

1h = SWB1 PG is NOT part of power good tree of GPO3 pin and is ignored.
0 LDOA3_MSK R/W 0h

0h = LDOA3 PG is part of power good tree of GPO3 pin.

1h = LDOA3 PG is NOT part of power good tree of GPO3 pin and is ignored.

5.9.45 MISCSYSPG Register (offset = ACh) [reset = FFh]

MISCSYSPG is shown in Figure 5-58 and described in Table 5-52.

Return to Summary Table.

Figure 5-58 MISCSYSPG Register
7 6 5 4 3 2 1 0
GPO1_CTL3_MSK GPO1_ CTL6_MSK GPO4_CTL3_MSK GPO4_ CTL6_MSK GPO2_CTL3_MSK GPO2_CTL6_MSK GPO3_CTL3_MSK GPO3_CTL6_MSK
R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h R/W-1h

Table 5-52 MISCSYSPG Field Descriptions

Bit Field Type Reset Description
7 GPO1_CTL3_MSK R/W 1h

0h = CTL3 pin status is part of power good tree of GPO1 pin.

1h = CTL3 pin status is NOT part of power good tree of GPO1 pin.
6 GPO1_CTL6_MSK R/W 1h

0h = CTL6 pin status is part of power good tree of GPO1 pin.

1h = CTL6 pin status is NOT part of power good tree of GPO1 pin.
5 GPO4_CTL3_MSK R/W 1h

0h = CTL3 pin status is part of power good tree of GPO4 pin.

1h = CTL3 pin status is NOT part of power good tree of GPO4 pin.
4 GPO4_CTL6_MSK R/W 1h

0h = CTL6 pin status is part of power good tree of GPO4 pin.

1h = CTL6 pin status is NOT part of power good tree of GPO4 pin.
3 GPO2_CTL3_MSK R/W 1h

0h = CTL3 pin status is part of power good tree of GPO2 pin.

1h = CTL3 pin status is NOT part of power good tree of GPO2 pin.
2 GPO2_CTL6_MSK R/W 1h

0h = CTL6 pin status is part of power good tree of GPO2 pin.

1h = CTL6 pin status is NOT part of power good tree of GPO2 pin.
1 GPO3_CTL3_MSK R/W 1h

0h = CTL3 pin status is part of power good tree of GPO3 pin.

1h = CTL3 pin status is NOT part of power good tree of GPO13pin.
0 GPO3_CTL6_MSK R/W 1h

0h = CTL6 pin status is part of power good tree of GPO3 pin.

1h = CTL6 pin status is NOT part of power good tree of GPO3 pin.

5.9.46 LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = 7Dh]

LDOA1CTRL is shown in Figure 5-59 and described in Table 5-53.

Return to Summary Table.

Figure 5-59 LDOA1CTRL Register
7 6 5 4 3 2 1 0
LDOA1_DISCHG[1:0] LDOA1_SDWN_CONFIG LDOA1_VID[3:0] LDOA1_EN
R/W-1h R/W-1h R/W-Eh R/W-1h

Table 5-53 LDOA1CTRL Field Descriptions

Bit Field Type Reset Description
7-6 LDOA1_DISCHG[1:0] R/W 1h

LDOA1 discharge resistance

0h = no discharge

1h = 100 Ω

2h = 200 Ω

3h = 500 Ω
5 LDOA1_SDWN_CONFIG R/W 1h

Control for Disabling LDOA1 during Emergency Shutdown

0h = LDOA1 will turn off during Emergency Shutdown for factory-programmable duration of 1 ms, 5 ms, 10 ms, or 100 ms.

1h = LDOA1 is controlled by LDOA1_EN bit only.
4-1 LDOA1_VID[3:0] R/W Eh

This field sets the LDOA1 regulator output regulation voltage. See Table 5-4 for VOUT options.
0 LDOA1_EN R/W 1h

LDOA1 Enable Bit.

0h = Disable.

1h = Enable.

5.9.47 PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0h]

PG_STATUS1 is shown in Figure 5-60 and described in Table 5-54.

Return to Summary Table.

Figure 5-60 PG_STATUS1 Register
7 6 5 4 3 2 1 0
LDOA2_PGOOD SWA1_PGOOD BUCK6_PGOOD BUCK5_PGOOD BUCK4_PGOOD BUCK3_PGOOD BUCK2_PGOOD BUCK1_PGOOD
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 5-54 PG_STATUS1 Field Descriptions

Bit Field Type Reset Description
7 LDOA2_PGOOD R 0h

LDOA2 power good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.
6 SWA1_PGOOD R 0h

SWA1 power good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.
5 BUCK6_PGOOD R 0h

BUCK6 power good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.
4 BUCK5_PGOOD R 0h

BUCK5 power good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.

3 BUCK4_PGOOD R 0h

BUCK4 power good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.
2 BUCK3_PGOOD R 0h

BUCK3 power good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.
1 BUCK2_PGOOD R 0h

BUCK2 power good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.
0 BUCK1_PGOOD R 0h

BUCK1 power good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.

5.9.48 PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0h]

PG_STATUS2 is shown in Figure 5-61 and described in Table 5-55.

Return to Summary Table.

Figure 5-61 PG_STATUS2 Register
7 6 5 4 3 2 1 0
RESERVED LDO5_PGOOD LDOA1_PGOOD VTT_PGOOD SWB2_PGOOD SWB1_PGOOD LDOA3_PGOOD
R-0h R-0h R-0h R-0h R-0h R-0h R-0h

Table 5-55 PG_STATUS2 Field Descriptions

Bit Field Type Reset Description
7-6 RESERVED R 0h
5 LDO5_PGOOD R 0h

LDO5 Power Good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.
4 LDOA1_PGOOD R 0h

LDOA1 Power Good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.

3 VTT_PGOOD R 0h

VTT LDO Power Good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.
2 SWB2_PGOOD R 0h

SWB2 Power Good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.

1 SWB1_PGOOD R 0h

SWB1 Power Good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.
0 LDOA3_PGOOD R 0h

LDOA3 Power Good status.

0h = The output is not in target regulation range.

1h = The output is in target regulation range.

5.9.49 PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0h]

PWR_FAULT_STATUS1 is shown in Figure 5-62 and described in Table 5-56.

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Figure 5-62 PWR_FAULT_STATUS1 Register
7 6 5 4 3 2 1 0
LDOA2_PWRFLT SWA1_PWRFLT BUCK6_PWRFLT BUCK5_PWRFLT BUCK4_PWRFLT BUCK3_PWRFLT BUCK2_PWRFLT BUCK1_PWRFLT
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 5-56 PWR_FAULT_STATUS1 Field Descriptions

Bit Field Type Reset Description
7 LDOA2_PWRFLT R 0h

This fields indicates that LDOA2 has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.
6 SWA1_PWRFLT R 0h

This fields indicates that SWA1 has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.
5 BUCK6_PWRFLT R 0h

This fields indicates that BUCK6 has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.
4 BUCK5_PWRFLT R 0h

This fields indicates that BUCK5 has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.
3 BUCK4_PWRFLT R 0h

This fields indicates that BUCK4 has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.
2 BUCK3_PWRFLT R 0h

This fields indicates that BUCK3 has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.
1 BUCK2_PWRFLT R 0h

This fields indicates that BUCK2 has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.
0 BUCK1_PWRFLT R 0h

This fields indicates that BUCK1 has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.

5.9.50 PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0h]

PWR_FAULT_STATUS2 is shown in Figure 5-63 and described in Table 5-57.

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Figure 5-63 PWR_FAULT_STATUS2 Register
7 6 5 4 3 2 1 0
RESERVED LDOA1_PWRFLT VTT_PWRFLT SWB2_PWRFLT SWB1_PWRFLT LDOA3_PWRFLT
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 5-57 PWR_FAULT_STATUS2 Field Descriptions

Bit Field Type Reset Description
7-5 RESERVED R 0h
4 LDOA1_PWRFLT R/W 0h

This fields indicates that LDOA1 has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.
3 VTT_PWRFLT R/W 0h

This fields indicates that VTT LDO has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.
4 SWB2_PWRFLT R/W 0h

This fields indicates that SWB2 has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.
3 SWB1_PWRFLT R/W 0h

This fields indicates that SWB1 has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.
0 LDOA3_PWRFLT R/W 0h

This fields indicates that LDOA3 has lost its regulation.

0h = No Fault.

1h = Power fault has occurred. The host to write 1 to clear.

5.9.51 TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0h]

TEMPCRIT is shown in Figure 5-64 and described in Table 5-58.

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Asserted when an internal temperature sensor detects rise of die temperature above the CRITICAL temperature threshold (TCRIT). There are 5 temperature sensors across the die.

Figure 5-64 TEMPCRIT Register
7 6 5 4 3 2 1 0
RESERVED DIE_CRIT VTT_CRIT TOP-RIGHT_CRIT TOP-LEFT_CRIT BOTTOM-RIGHT_CRIT
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 5-58 TEMPCRIT Field Descriptions

Bit Field Type Reset Description
7-5 RESERVED R 0h
4 DIE_CRIT R/W 0h

Temperature of rest of die has exceeded TCRIT.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.
3 VTT_CRIT R/W 0h

Temperature of VTT LDO has exceeded TCRIT.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.
2 TOP-RIGHT_CRIT R/W 0h

Temperature of die Top-Right has exceeded TCRIT. Top-Right corner of die from top view given pin1 is in Top-Left corner.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.
1 TOP-LEFT_CRIT R/W 0h

Temperature of die Top-Left has exceeded TCRIT.Top-Left corner of die from top view given pin1 is in Top-Left corner.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.
0 BOTTOM-RIGHT_CRIT R/W 0h

Temperature of die Bottom-Right has exceeded TCRIT. Bottom-Right corner of die from top view given pin1 is in Top-Left corner.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.

5.9.52 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0h]

TEMPHOT is shown in Figure 5-65 and described in Table 5-59.

Return to Summary Table.

Asserted when an internal temperature sensor detects rise of die temperature above the HOT temperature threshold (THOT). There are 5 temperature sensors across the die.

Figure 5-65 TEMPHOT Register
7 6 5 4 3 2 1 0
RESERVED DIE_HOT VTT_HOT TOP-RIGHT_HOT TOP-LEFT_HOT BOTTOM-RIGHT_HOT
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 5-59 TEMPHOT Field Descriptions

Bit Field Type Reset Description
7-5 RESERVED R 0h
4 DIE_HOT R/W 0h

Temperature of rest of die has exceeded THOT.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.
3 VTT_HOT R/W 0h

Temperature of VTT LDO has exceeded THOT.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.
2 TOP-RIGHT_HOT R/W 0h

Temperature of Top-Right has exceeded THOT. Top-Right corner of die from top view given pin1 is in Top-Left corner.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.
1 TOP-LEFT_HOT R/W 0h

Temperature of Top-Left has exceeded THOT. Top-Left corner of die from top view given pin1 is in Top-Left corner.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.
0 BOTTOM-RIGHT_HOT R/W 0h

Temperature of Bottom-Right has exceeded THOT. Bottom-Right corner of die from top view given pin1 is in Top-Left corner.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.

5.9.53 OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0h]

OC_STATUS is shown in Figure 5-66 and described in Table 5-60.

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Asserted when overcurrent condition is detected from a LSD FET.

Figure 5-66 OC_STATUS Register
7 6 5 4 3 2 1 0
RESERVED BUCK6_OC BUCK2_OC BUCK1_OC
R-0h R/W-0h R/W-0h R/W-0h

Table 5-60 OC_STATUS Field Descriptions

Bit Field Type Reset Description
7-3 RESERVED R 0h
2 BUCK6_OC R/W 0h

BUCK6 LSD FET overcurrent has been detected.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.
1 BUCK2_OC R/W 0h

BUCK2 LSD FET overcurrent has been detected.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.
0 BUCK1_OC R/W 0h

BUCK1 LSD FET overcurrent has been detected.

0h = Not asserted.

1h = Asserted. The host to write 1 to clear.