ZHCSIN0 August   2018 TPS62810-Q1 , TPS62812-Q1

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      原理图
      2.      效率与输出电流间的关系;VOUT = 3.3V;PWM/PFM;fS = 2.25MHz
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Schematic
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Precise Enable
      2. 9.3.2 COMP/FSET
      3. 9.3.3 MODE / SYNC
      4. 9.3.4 Spread Spectrum Clocking (SSC); optional
      5. 9.3.5 Undervoltage Lockout (UVLO)
      6. 9.3.6 Power Good Output (PG)
      7. 9.3.7 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Pulse Width Modulation (PWM) Operation
      2. 9.4.2 Power Save Mode Operation (PWM/PFM)
      3. 9.4.3 100% Duty-Cycle Operation
      4. 9.4.4 Current Limit and Short Circuit Protection
      5. 9.4.5 Fold-back Current Limit and Short Circuit Protection
      6. 9.4.6 Output Discharge
      7. 9.4.7 Soft Start / Tracking (SS/TR)
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Programming the Output Voltage
      2. 10.1.2 External Component Selection
      3. 10.1.3 Inductor Selection
      4. 10.1.4 Capacitor Selection
        1. 10.1.4.1 Input Capacitor
        2. 10.1.4.2 Output Capacitor
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Voltage Tracking
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 器件支持
      1. 13.1.1 第三方产品免责声明
    2. 13.2 文档支持
      1. 13.2.1 相关文档
    3. 13.3 相关链接
    4. 13.4 接收文档更新通知
    5. 13.5 社区资源
    6. 13.6 商标
    7. 13.7 静电放电警告
    8. 13.8 术语表
    9. 13.9 勘误
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
  • RWY|9
散热焊盘机械数据 (封装 | 引脚)
订购信息

Electrical Characteristics

over operating junction temperature (TJ = -40 °C to +150 °C) and VIN = 2.75 V to 6 V.
Typical values at VIN = 5 V and TJ = 25 °C. (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Operating Quiescent Current EN = high, IOUT= 0 mA, Device not switching,
TJ= 125 °C
21 µA
IQ Operating Quiescent Current EN = high, IOUT= 0 mA, Device not switching 15 30 µA
ISD Shutdown Current EN = 0 V, at TJ= 125 °C 18 µA
ISD Shutdown Current EN = 0 V, Nominal value at TJ= 25 °C,
Max value at TJ= 150 °C
1.5 26 µA
VUVLO Undervoltage Lockout Threshold Rising Input Voltage 2.5 2.6 2.75 V
Falling Input Voltage 2.3 2.5 2.6 V
TSD Thermal Shutdown Temperature Rising Junction Temperature 155 170 185 °C
Thermal Shutdown Hysteresis 15
CONTROL (EN, SS/TR, PG, MODE/SYNC, COMP/FSET)
VIH High Level Input Voltage for MODE/SYNC Pin 1.1 V
VIL Low Level Input Voltage for MODE/SYNC Pin 0.3 V
fSYNC Frequency Range on MODE/SYNC Pin for Synchronization requires a resistor from COMP/FSET to GND, see application section 1.8 4 MHz
duty cycle of synchronization signal at MODE/SYNC Pin 40% 50% 60%
Time to Lock to External Frequency 50 µs
VIH Input Threshold Voltage for EN pin; Rising Edge 1.06 1.1 1.15 V
VIL Input Threshold Voltage for EN pin; Falling Edge 0.96 1.0 1.05 V
ILKG Input Leakage Current for EN, MODE/SYNC VIH = VIN or VIL= GND 125 nA
resistance from COMP/FSET to GND for logic low internal frequency setting with f = 2.25 MHz 0 2.5
voltage on COMP/FSET for logic high internal frequency setting with f = 2.25 MHz VIN V
VTH_PG UVP Power Good Threshold Voltage; dc Level Rising (%VOUT) 92% 95% 98%
UVP Power Good Threshold Voltage; dc Level Falling (%VOUT) 87% 90% 93%
OVP Power Good Threshold; dc Level Rising (%VOUT) 107% 110% 113%
OVP Power Good Threshold; dc Level Falling (%VOUT) 104% 107% 111%
power good de-glitch time for a high level to low level transition on the power good output 40 µs
VOL_PG Power Good Output Low Voltage IPG = 2 mA 0.07 0.3 V
ILKG_PG Input Leakage Current (PG) VPG = 5 V 100 nA
ISS/TR SS/TR Pin Source Current 2.1 2.5 2.8 µA
Tracking Gain VFB / VSS/TR 1
Tracking Offset feedback voltage with VSS/TR = 0 V 17 mV
POWER SWITCH
RDS(ON) High-Side MOSFET ON-Resistance VIN ≥ 5 V 37 60
Low-Side MOSFET ON-Resistance VIN ≥ 5 V 15 35
High-Side MOSFET leakage current TJ = 85 °C 0.5 µA
High-Side MOSFET leakage current 0.1 2 µA
Low-Side MOSFET leakage current TJ = 85 °C 2 µA
Low-Side MOSFET leakage current 12 µA
ILIMH High-Side MOSFET Current Limit DC value; for TPS62810-Q1; VIN = 3 V to 6 V 4.8 5.6 6.4 A
ILIMH High-Side MOSFET Current Limit DC value; for TPS62813-Q1; VIN = 3 V to 6 V 3.9 4.5 5.1 A
ILIMH High-Side MOSFET Current Limit DC value; for TPS62812-Q1; VIN = 3 V to 6 V 2.9 3.4 3.9 A
ILIMH High-Side MOSFET Current Limit DC value; for TPS62811-Q1; VIN = 3 V to 6 V 2.1 2.6 3.0 A
ILIMNEG Negative Current Limit DC value -1.8 A
fS PWM Switching Frequency Range see the FSET pin functionality about setting the switching frequency 1.8 2.25 4 MHz
PWM Switching Frequency with COMP/FSET tied to VIN or GND 2.025 2.25 2.475 MHz
PWM Switching Frequency Tolerance using a resistor from COMP/FSET to GND -15% 15%
ton,min Minimum on-time of high side FET TJ = -40 °C to 125 °C, VIN = 3.3 V 50 75 ns
ton,min Minimum on-time of low side FET 30 ns
OUTPUT
VFB Feedback Voltage 0.6 V
ILKG_FB Input Leakage Current (FB) VFB = 0.6 V 1 70 nA
VFB Feedback Voltage Accuracy VIN ≥ VOUT + 1 V PWM mode -1% 1%
VIN ≥ VOUT + 1 V;
VOUT ≥ 1.5 V
PFM mode;
Co,eff ≥ 22 µF,
L = 0.47 µH
-1% 2%
1 V ≤ VOUT < 1.5 V PFM mode;
Co,eff ≥ 47 µF,
L = 0.47 µH
-1% 2.5%
VFB Feedback Voltage Accuracy with Voltage Tracking VIN ≥ VOUT + 1 V;
VSS/TR = 0.3 V
PWM mode -2% 5%
Load Regulation PWM mode operation 0.025 %/A
Line Regulation PWM mode operation, IOUT = 1 A, VIN ≥ VOUT + 1 V 0.02 %/V
Output Discharge Resistance 50 Ω
tdelay Start-up Delay Time IOUT = 0 mA, Time from EN=high to start switching; VIN applied already 135 200 450 µs
tdelay Start-up Delay Time IOUT = 0 mA, Time from EN=high to start switching; VIN applied already; VIN ≥ 3.1 V 390 µs
tramp Ramp time; SS/TR Pin Open IOUT = 0 mA, Time from first switching pulse until 95% of nominal output voltage; device not in current limit 100 150 200 µs