ZHCSEW2B March   2016  – December 2017 TPS564208

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Adaptive On-Time Control and PWM Operation
      2. 7.3.2 Soft Start and Pre-Biased Soft Start
      3. 7.3.3 Current Protection
      4. 7.3.4 Undervoltage Lockout (UVLO) Protection
      5. 7.3.5 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Standby Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Resistors Selection
        3. 8.2.2.3 Output Filter Selection
        4. 8.2.2.4 Input Capacitor Selection
        5. 8.2.2.5 Bootstrap Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 开发支持
      1. 11.1.1 使用 WEBENCH® 工具创建定制设计方案
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The device is a typical step-down DC-DC converter for converting a higher dc voltage to a lower dc voltage with a maximum available output current of 4 A. The following design procedure can be used to select component values for the TPS564208. Alternately, the WEBENCH® software may be used to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. This section presents a simplified discussion of the design process.

8.2 Typical Application

The application schematic in Figure 14 shows the TPS564208 4.5-V to 17-V input, 1.05-V output converter design meeting the requirements for 4-A output. This circuit is available as the evaluation module (EVM). The sections provide the design procedure.

Figure 14. TPS564208 1.05-V, 4-A Reference Design

8.2.1 Design Requirements

Table 1 shows the design parameters for this application.

Table 1. Design Parameters

PARAMETER EXAMPLE VALUE
Input voltage range 4.5 to 17 V
Output voltage 1.05 V
Transient response, 2-A load step ΔVout = ±5%
Input ripple voltage 400 mV
Output ripple voltage 30 mV
Output current rating 4 A
Operating frequency 560 kHz

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPS564208 device with the WEBENCH® Power Designer.

  1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
  2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
  3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability.

In most cases, these actions are available:

  • Run electrical simulations to see important waveforms and circuit performance
  • Run thermal simulations to understand board thermal performance
  • Export customized schematic and layout into popular CAD formats
  • Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Output Voltage Resistors Selection

The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends to use 1% tolerance or better divider resistors. Start by using to calculate VOUT.

To improve efficiency at very light loads consider using larger value resistors. However, using too high of resistance causes the circuit to be more susceptible to noise; and, voltage errors from the VFB input current will be more noticeable.

Equation 1. TPS564208 Eq_Vout_SLVSDJ7.gif

8.2.2.3 Output Filter Selection

The LC filter used as the output filter has double pole at:

Equation 2. TPS564208 Eq_03_SLVSD90.gif

At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the device. The low frequency phase is 180°. At the output filter pole frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high frequency zero that reduces the gain roll off to –20 dB per decade and increases the phase to 90° one decade above the zero frequency. The inductor and capacitor for the output filter must be selected so that the double pole of Equation 2 is located below the high frequency zero but close enough that the phase boost provided be the high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the values recommended in Table 2.

Table 2. Recommended Component Values

OUTPUT VOLTAGE (V) R1 (kΩ) R2 (kΩ) L1 (µH) C8 + C9 (µF)
MIN TYP MAX
1 3.09 10.0 1.5 2.2 4.7 20 to 68
1.05 3.74 10.0 1.5 2.2 4.7 20 to 68
1.2 5.76 10.0 1.5 2.2 4.7 20 to 68
1.5 9.53 10.0 1.5 2.2 4.7 20 to 68
1.8 13.7 10.0 1.5 2.2 4.7 20 to 68
2.5 22.6 10.0 2.2 2.2 4.7 20 to 68
3.3 33.2 10.0 2.2 2.2 4.7 20 to 68
5 54.9 10.0 3.3 3.3 4.7 20 to 68
6.5 75 10.0 3.3 3.3 4.7 20 to 68

The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 3, Equation 4, and Equation 5. The inductor saturation current rating must be greater than the calculated peak current and the RMS or heating current rating must be greater than the calculated RMS current.

Use 560 kHz for ƒSW. Make sure the chosen inductor is rated for the peak current of Equation 4 and the RMS current of Equation 6.

Equation 3. TPS564208 Eq_04_SLVSD90.gif
Equation 4. TPS564208 Eq_05_SLVSD90.gif
Equation 5. TPS564208 Eq_06_SLVSD90.gif

For this design example, the calculated peak current is 4.4 A and the calculated RMS current is 4 A. The inductor used is a WE 74431122 with a peak current rating of 13 A and an RMS current rating of 9 A.

The capacitor value and ESR determines the amount of output voltage ripple. The TPS564208 is intended for use with ceramic or other low ESR capacitors. Recommended values range from 20 µF to 68 µF. Use Equation 6 to determine the required RMS current rating for the output capacitor.

Equation 6. TPS564208 Eq_07_SLVSD90.gif

For this design two TDK C3216X5R0J226M 22-µF output capacitors are used. The typical ESR is 2 mΩ each. The calculated RMS current is 0.286 A and each output capacitor is rated for 4 A.

8.2.2.4 Input Capacitor Selection

The TPS564208 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. An additional 0.1-µF capacitor (C3) from pin 3 to ground is optional to provide additional high frequency filtering. The capacitor voltage rating needs to be greater than the maximum input voltage.

8.2.2.5 Bootstrap Capacitor Selection

A 0.1-µF ceramic capacitor must be connected between the VBST to SW pin for proper operation. TI recommends to use a ceramic capacitor.

8.2.3 Application Curves

TPS564208 D015_SLVSDG0.gif
VIN = 5 V VOUT1 = 1.05 V
Figure 15. TPS564208 Load Regulation, VIN = 5 V
TPS564208 D016_SLVSDG0.gif
IOUT = 1 A
Figure 17. TPS564208 Line Regulation
TPS564208 input_ripple1_SLVSDG0.gif
1 µs/div
Figure 19. TPS564208 Input Voltage Ripple
TPS564208 output_ripple_Iout_2A_SLVSDG0.gif
1 µs/div
Figure 21. TPS564208 Output Voltage Ripple, IOUT 2 A
TPS564208 transient_response_0p1_2A_SLVSDG0.gif
100 µs/div
Figure 23. TPS564208 Transient Response 0.1 to 2 A
TPS564208 transient_response_2_4A_SLVSDG0.gif
100 µs/div
Figure 25. TPS564208 Transient Response, 2 to 4 A
TPS564208 startup_relative_to_EN_SLVSDG0.gif
400 µs/div
Figure 27. TPS564208 Startup Relative to EN
TPS564208 shutdown_relative_to_EN_SLVSDG0.gif
400 µs/div
Figure 29. TPS564208 Shutdown Relative to EN
TPS564208 D014_SLVSDG0.gif
VIN = 12 V VOUT1 = 1.05 V
Figure 16. TPS564208 Load Regulation, VIN = 12 V
TPS564208 D017_SLVSDG0.gif
Figure 18. TPS564208 Efficiency, Vout = 1.05 V
TPS564208 output_ripple_no_load_SLVSDG0.gif
1 µs/div
Figure 20. TPS564208 Output Voltage Ripple, No Load
TPS564208 output_ripple_Iout_4A_SLVSDG0.gif
1 µs/div
Figure 22. TPS564208 Output Voltage Ripple, IOUT 4 A
TPS564208 transient_response_1_3A_SLVSDG0.gif
100 µs/div
Figure 24. TPS564208 Transient Response, 1 to 3 A
TPS564208 startup_relative_to_VIN_SLVSDG0.gif
2 ms/div
Figure 26. TPS564208 Startup Relative to VIN
TPS564208 shutdown_relative_to_VIN_SLVSDG0.gif
20 ms/div
Figure 28. TPS564208 Shutdown Relative to VIN