ZHCSEW2B March   2016  – December 2017 TPS564208

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Adaptive On-Time Control and PWM Operation
      2. 7.3.2 Soft Start and Pre-Biased Soft Start
      3. 7.3.3 Current Protection
      4. 7.3.4 Undervoltage Lockout (UVLO) Protection
      5. 7.3.5 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Standby Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Resistors Selection
        3. 8.2.2.3 Output Filter Selection
        4. 8.2.2.4 Input Capacitor Selection
        5. 8.2.2.5 Bootstrap Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 开发支持
      1. 11.1.1 使用 WEBENCH® 工具创建定制设计方案
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10 Layout

10.1 Layout Guidelines

  1. VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of advantage from the view point of heat dissipation.
  2. The input capacitor and output capacitor should be placed as close to the device as possible to minimize trace impedance.
  3. Provide sufficient vias for the input capacitor and output capacitor.
  4. Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
  5. Do not allow switching current to flow under the device.
  6. A separate VOUT path should be connected to the upper feedback resistor.
  7. Make a Kelvin connection to the GND pin for the feedback path.
  8. Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has ground shield.
  9. The trace of the VFB node should be as small as possible to avoid noise coupling.
  10. The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its trace impedance.

10.2 Layout Example

TPS564208 Layout_SLVSD90.gif Figure 30. TPS564208 Layout Example