10.1 Layout Guidelines

• For the maximum effectiveness from C9, place it near the VDD pin of the controller. Excessive high frequency noise on VDD during switching degrades overall regulation as the load increases.
• Keep the output loop (Q1-D1-C12-R11) as small as possible. A larger loop can degrade current limit accuracy and increase rediated emissions.
• For best current limit accuracy keep the ISNS filter components C10 and R10 near the ISNS and GND pins.
• Avoid connecting traces carrying large AC currents through a ground plane. Instead, use PCB traces on the top layer to conduct the AC current and use the ground plane as a noise shield.
• Split the ground plane as necessary to keep noise away from the TPS40210-EP and noise sensitive areas such as components connected to the RC pin, FB pin, COMP pin and SS pin. Also keep these noise sensitive components close to the TPS40210-EP IC.
• Keep C7 near the BP and GND pins to provide good bypass for the BP regulator.
• The GDRV trace should be as close as possible to the power FET gate to minimize parisitic resistance and inductance in the trace. The parasitics should also be minimized in the return path from the source of the MOSFET, through the sense resistor and back to the GND pin.
• Keep the SW node as physically small as possible to minimize parasitic capacitance and radiated emissions.
• For good output voltage regulation, Kelvin connections should be brought from the load to the top FB resistor R7.

10.2 Layout Example

Figure 35. Component Placement

Figure 36. Top Copper

Figure 37. Bottom Copper Viewed from Top

Figure 38. Internal 1 Copper Viewed from Top

Figure 39. Internal 2 Copper Viewed from Top