ZHCS329B July   2011  – April 2015

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Pin (SENSE)
      2. 8.3.2 Enable Pin (ENABLE)
      3. 8.3.3 Output Pin (SENSE_OUT)
      4. 8.3.4 Output Delay Time Pin (CT)
      5. 8.3.5 Immunity To Sense Pin Voltage Transients
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(min))
      2. 8.4.2 Below VDD(min) (V(POR) < VDD < VDD(min))
      3. 8.4.3 Below Power-On Reset (VDD < V(POR))
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Single-Rail Monitoring
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Multiple Voltage Monitoring Sequential Delay
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
      3. 9.2.3 Multiple Voltage Monitoring Minimum Delay
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Voltage Sequencing
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 开发支持
        1. 12.1.1.1 评估模块
        2. 12.1.1.2 Spice 模型
      2. 12.1.2 器件命名规则
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

DRY Package: TPS3895, TPS3897
6-Pin USON
Top View
TPS389 po_dry_3895_7_bvs172.gif
DRY Package: TPS3896, TPS3898
6-Pin USON
Top View
TPS389 po_dry_3896_8_bvs172.gif

Pin Functions

PIN I/O DESCRIPTION
NAME USON
TPS3895/
TPS3897		 TPS3896/
TPS3898
CT 5 5 I Capacitor-adjustable delay. The CT pin offers a user-adjustable delay time. Connecting this pin to a ground referenced capacitor sets the delay time for SENSE rising above
0.5 V to SENSE_OUT asserting (or ENABLE asserting to SENSE_OUT asserting for A version devices).
tpd(r) (s) = [CCT (µF) × 4] + 40 µs
ENABLE 1 — I Active high input. Driving ENABLE low immediately makes SENSE_OUT go low, independent of V(SENSE). With V(SENSE) already above VIT+, drive ENABLE high to make SENSE_OUT go high after the capacitor-adjustable delay time (A version) or 0.2 µs (P version).
ENABLE — 1 I Active low input. Driving ENABLE high immediately makes SENSE_OUT go high, independent of V(SENSE). With V(SENSE) already above VIT+, drive ENABLE low to make SENSE_OUT go low after the capacitor-adjustable delay time (A version) or 0.2 µs (P version).
GND 2 2 — Ground
SENSE 3 3 I This pin is connected to the voltage that is monitored with the use of an external resistor. The output asserts after the capacitor-adjustable delay time when V(SENSE) rises above 0.5 V and ENABLE is asserted. The output deasserts after a minimal propagation delay (16 µs) when V(SENSE) falls below VIT+ – Vhys.
SENSE_OUT 4 — O SENSE_OUT is an open-drain and push-pull output that is immediately driven low after V(SENSE) falls below (VIT+ – Vhys) or the ENABLE input is low. SENSE_OUT goes high after the capacitor-adjustable delay time when V(SENSE) is greater than VIT+ and the ENABLE pin is high. Open-drain devices (TPS3897/8) can be pulled up to 18 V independent of VCC; pullup resistors are required for these devices.
SENSE_OUT — 4 O SENSE_OUT is an open-drain and push-pull output that is immediately driven high after V(SENSE) falls below (VIT+ – Vhys) or the ENABLE input is high. SENSE_OUT goes low after the capacitor-adjustable delay time when V(SENSE) is greater than VIT+ and the ENABLE pin is low. Open-drain devices (TPS3897/8) can be pulled up to 18 V independent of VCC; pullup resistors are required for these devices.
VCC 6 6 I Supply voltage input. Connect a 1.7-V to 6.5-V supply to VCC to power the device. It is good analog design practice to place a 0.1-µF ceramic capacitor close to this pin.