ZHCSF70A March   2016  – May 2016 TPS3890

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 User-Configurable RESET Delay Time
      2. 8.3.2 Manual Reset (MR) Input
      3. 8.3.3 RESET Output
      4. 8.3.4 SENSE Input
        1. 8.3.4.1 Immunity to SENSE Pin Voltage Transients
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VDD(min))
      2. 8.4.2 Above Power-On-Reset But Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 8.4.3 Below Power-On-Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档　
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

DSE Package
6-Pin WSON
Top View

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
5 CT — The CT pin offers a user-adjustable delay time. Connecting this pin to a ground-referenced capacitor sets the RESET delay time to deassert.
tPD(r) (sec) = CCT (µF) × 1.07 + 25 µs (nom).
2 GND — Ground
3 MR I Driving the manual reset pin (MR) low causes RESET to go low (assert).
6 RESET O RESET is an open-drain output that is driven to a low-impedance state when either the MR pin is driven to a logic low or the monitored voltage on the SENSE pin is lower than the negative threshold voltage (VITN). RESET remains low (asserted) for the delay time period after both MR is set to a logic high and the SENSE input is above VITP. A pullup resistor from 10 kΩ to 1 MΩ can be used on this pin.
1 SENSE I This pin is connected to the voltage to be monitored. When the voltage on SENSE falls below the negative threshold voltage VITN, RESET goes low (asserts). When the voltage on SENSE rises above the positive threshold voltage VITP, RESET goes high (deasserts).
4 VDD I Supply voltage pin. Good analog design practice is to place a 0.1-µF ceramic capacitor close to this pin.