ZHCSAL0D March   2016  – August 2020 TPD3S716-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—AEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 ESD Ratings—ISO Specification
    5. 6.5 Recommended Operating Conditions
    6. 6.6 Thermal Information
    7. 6.7 Electrical Characteristics
    8. 6.8 Timing Characteristics
    9. 6.9 Typical Characteristics
  7. Parameter Measurement Information
    1.     18
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  AEC-Q100 Qualified
      2. 8.3.2  Short-to-Battery and Short-to-Ground Protection on VBUS_CON
      3. 8.3.3  Short-to-Battery and Short-to-VBUS Protection on VD+, VD–
      4. 8.3.4  ESD Protection on VBUS_CON, VD+, VD–
      5. 8.3.5  Low RON nFET VBUS Switch
      6. 8.3.6  High Speed Data Switches
      7. 8.3.7  Adjustable Hiccup Current Limit up to 2.4-A
      8. 8.3.8  Fast Over-Voltage Response Time
      9. 8.3.9  Independent VBUS and Data Enable Pins for Configuring both Host and Client/OTG Mode
      10. 8.3.10 Fault Output Signal
      11. 8.3.11 Thermal Shutdown Feature
      12. 8.3.12 16-Pin SSOP Package
      13. 8.3.13 Reverse Current Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 Overvoltage Condition
      3. 8.4.3 Overcurrent Condition
      4. 8.4.4 Short-Circuit Condition
      5. 8.4.5 Device Logic Table
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Short-to-Battery Tolerance
        2. 9.2.2.2 Maximum Current on VBUS
        3. 9.2.2.3 Power Dissipation and Junction Temperature
        4. 9.2.2.4 USB Data Rate
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 VBUS Path
    2. 10.2 VIN Pin
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Layout Optimized for Thermal Performance
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 静电放电警告
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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订购信息

Power Dissipation and Junction Temperature

This section demonstrates how to analyze the power dissipation and junction temperature of the TPD3S716-Q1 to validate that the application requirements of an IVBUS operating current level of 1.5 A and a maximum operating ambient temperature of 105 °C can be met.

It is good design practice to estimate power dissipation and maximum expected junction temperature of TPD3S716-Q1. This is important to insure the device does not go into thermal shutdown in normal operation and that the long term reliability of the device is maintained. Using Equation 4 to Equation 6, the system designer can control choices of the device's proximity to other power dissipating devices and the design of the printed circuit board (PCB). These have a direct influence on maximum junction temperature. Other factors, such as airflow and maximum ambient temperature, are often determined by system considerations. It is important to remember that these calculations do not include the effects of adjacent heat sources, and enhanced or restricted air flow. Addition of extra PCB copper area around these devices is recommended to reduce the thermal impedance and maintain the junction temperature as low as practical.

For TPD3S716-Q1, the operating junction temperature must be kept below 150°C in order to prevent the device from going into thermal shutdown. Equation 4 is used to calculate the junction temperature of the device:

Equation 4. TJ = TA + [(IOUT2 × RON) × RθJA]

where

  • IOUT = Rated OUT pin current (A)
  • RON = Power path on-resistance at an assumed TJ (Ω)
  • TA = Maximum ambient temperature (°C)
  • TJ = Maximum junction temperature (°C)
  • RθJA = Thermal resistance (°C/W)

This application example requires an IVBUS operating current level of 1.5 A. TPD3S716-Q1 has maximum junction temperature derating requirements depending on the maximum operating current of the device according to Equation 5:

Equation 5. TJ(MAX) = –15.6 × (IVBUS(MAX OPERATING)) + 161.5 (°C)

where

  • TJ(MAX) = Maximum allowed junction temperature (°C)
  • IVBUS(MAX OPERATING) = Maximum IVBUS operating current (A)

See Figure 9-7 for a plot of the reliability curve equation. Using this equation, 138.1°C is the maximum allowed junction temperature in this application.

This example requires a maximum operating ambient temperature of 105°C. To determine if this can be supported using Equation 4, the maximum VBUS path RON must be determined. Equation 6 calculates the maximum VBUS path RON possible for TPD3S716-Q1 for a given junction temperature:

Equation 6. RON(MAX) = (TJ + 183.15) / 2726.7 (Ω)

where

  • RON(MAX) = Maximum VBUS RON at a given junction temperature (Ω)
  • TJ = Device junction temperature (°C)

See Figure 9-8 for a plot of the maximum VBUS path RON vs. Junction Temperature curve. Using the above equation, the maximum VBUS RON possible for TPD3S716-Q1 at 138.1°C is RON(MAX) = 0.118 Ω.

Using the calculated parameters for this example and the standard datasheet RθJA for TPD3S716-Q1, the maximum operating ambient temperature possible in this example is TA = 111°C. Because this is greater than the application requirement of 105°C, TPD3S716-Q1 can safely be operated at 1.5 A with RθJA = 98.8 (°C/W). If the resulting ambient temperature in the above calculations resulted in a TA < 105 °C, methods for improving RθJA would need to be taken. See the Layout Optimized for Thermal Performance section for guidelines on improving RθJA for TPD3S716-Q1. The example given in the Layout Optimized for Thermal Performance yields an RθJA = 57 (°C/W). Excellent thermal performance of TPD3S716-Q1 can be achieved with the proper PCB layout.