ZHCSHE0 December 2017 TMS320F28377D-EP
|Power-up time (from COMPCTL[COMPDACE] to comparator ready)||10||µs|
|Comparator input (CMPINxx) range||0||VDDA||V|
|Input referred offset error||–20||20||mV|
|Hysteresis(1)||1x||12||CMPSS DAC LSB|
|Response time (delay from CMPINx input change to output on ePWM X-BAR or Output X-BAR)||Step response||21||60||ns|
|Ramp response (1.65 V/µs)||26|
|Ramp response (8.25 mV/µs)||30|
The CMPSS inputs must be kept below VDDA + 0.3 V to ensure proper functional operation. If a CMPSS input exceeds this level, an internal blocking circuit will isolate the internal comparator from the external pin until the external pin voltage returns below VDDA + 0.3 V. During this time, the internal comparator input will be floating and can decay below VDDA within approximately 0.5 µs. After this time, the comparator could begin to output an incorrect result depending on the value of the other comparator input.
Table 4-53 shows the CMPSS DAC static electrical characteristics. Figure 4-40 shows the CMPSS DAC static offset. Figure 4-41 shows the CMPSS DAC static gain. Figure 4-42 shows the CMPSS DAC static linearity.