ZHCS864M April   2009  – January 2019 TMS320F28030 , TMS320F28031 , TMS320F28032 , TMS320F28033 , TMS320F28034 , TMS320F28035

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Automotive
    3. 5.3  ESD Ratings – Commercial
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 TMS320F2803x Current Consumption at 60-MHz SYSCLKOUT
      2. 5.5.1     Reducing Current Consumption
      3. 5.5.2     Current Consumption Graphs (VREG Enabled)
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics
      1. 5.7.1 PN Package
      2. 5.7.2 PAG Package
      3. 5.7.3 RSH Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  Emulator Connection Without Signal Buffering for the MCU
    10. 5.10 Parameter Information
      1. 5.10.1 Timing Parameter Symbology
      2. 5.10.2 General Notes on Timing Parameters
    11. 5.11 Test Load Circuit
    12. 5.12 Power Sequencing
      1. Table 5-3 Reset (XRS) Timing Requirements
      2. Table 5-4 Reset (XRS) Switching Characteristics
    13. 5.13 Clock Specifications
      1. 5.13.1 Device Clock Table
        1. Table 5-5 2803x Clock Table and Nomenclature (60-MHz Devices)
        2. Table 5-6 Device Clocking Requirements/Characteristics
        3. Table 5-7 Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics
      2. 5.13.2 Clock Requirements and Characteristics
        1. Table 5-8  XCLKIN Timing Requirements – PLL Enabled
        2. Table 5-9  XCLKIN Timing Requirements – PLL Disabled
        3. Table 5-10 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
    14. 5.14 Flash Timing
      1. Table 5-11 Flash/OTP Endurance for T Temperature Material
      2. Table 5-12 Flash/OTP Endurance for S Temperature Material
      3. Table 5-13 Flash/OTP Endurance for Q Temperature Material
      4. Table 5-14 Flash Parameters at 60-MHz SYSCLKOUT
      5. Table 5-15 Flash/OTP Access Timing
      6. Table 5-16 Flash Data Retention Duration
  6. 6Detailed Description
    1. 6.1 Overview
      1. 6.1.1  CPU
      2. 6.1.2  Control Law Accelerator (CLA)
      3. 6.1.3  Memory Bus (Harvard Bus Architecture)
      4. 6.1.4  Peripheral Bus
      5. 6.1.5  Real-Time JTAG and Analysis
      6. 6.1.6  Flash
      7. 6.1.7  M0, M1 SARAMs
      8. 6.1.8  L0 SARAM, and L1, L2, and L3 DPSARAMs
      9. 6.1.9  Boot ROM
        1. 6.1.9.1 Emulation Boot
        2. 6.1.9.2 GetMode
        3. 6.1.9.3 Peripheral Pins Used by the Bootloader
      10. 6.1.10 Security
      11. 6.1.11 Peripheral Interrupt Expansion (PIE) Block
      12. 6.1.12 External Interrupts (XINT1–XINT3)
      13. 6.1.13 Internal Zero Pin Oscillators, Oscillator, and PLL
      14. 6.1.14 Watchdog
      15. 6.1.15 Peripheral Clocking
      16. 6.1.16 Low-power Modes
      17. 6.1.17 Peripheral Frames 0, 1, 2, 3 (PFn)
      18. 6.1.18 General-Purpose Input/Output (GPIO) Multiplexer
      19. 6.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 6.1.20 Control Peripherals
      21. 6.1.21 Serial Port Peripherals
    2. 6.2 Memory Maps
    3. 6.3 Register Maps
    4. 6.4 Device Emulation Registers
    5. 6.5 VREG/BOR/POR
      1. 6.5.1 On-chip Voltage Regulator (VREG)
        1. 6.5.1.1 Using the On-chip VREG
        2. 6.5.1.2 Disabling the On-chip VREG
      2. 6.5.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit
    6. 6.6 System Control
      1. 6.6.1 Internal Zero Pin Oscillators
      2. 6.6.2 Crystal Oscillator Option
      3. 6.6.3 PLL-Based Clock Module
      4. 6.6.4 Loss of Input Clock (NMI Watchdog Function)
      5. 6.6.5 CPU-Watchdog Module
    7. 6.7 Low-power Modes Block
    8. 6.8 Interrupts
      1. 6.8.1 External Interrupts
        1. 6.8.1.1 External Interrupt Electrical Data/Timing
          1. Table 6-22 External Interrupt Timing Requirements
          2. Table 6-23 External Interrupt Switching Characteristics
    9. 6.9 Peripherals
      1. 6.9.1  Control Law Accelerator (CLA) Overview
      2. 6.9.2  Analog Block
        1. 6.9.2.1 Analog-to-Digital Converter (ADC)
          1. 6.9.2.1.1 Features
          2. 6.9.2.1.2 ADC Start-of-Conversion Electrical Data/Timing
            1. Table 6-28 External ADC Start-of-Conversion Switching Characteristics
          3. 6.9.2.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
            1. Table 6-29  ADC Electrical Characteristics
            2. Table 6-30  ADC Power Modes
            3. 6.9.2.1.3.1 Internal Temperature Sensor
              1. Table 6-31 Temperature Sensor Coefficient
            4. 6.9.2.1.3.2 ADC Power-Up Control Bit Timing
              1. Table 6-32 ADC Power-Up Delays
            5. 6.9.2.1.3.3 ADC Sequential and Simultaneous Timings
        2. 6.9.2.2 ADC MUX
        3. 6.9.2.3 Comparator Block
          1. 6.9.2.3.1 On-Chip Comparator/DAC Electrical Data/Timing
            1. Table 6-34 Electrical Characteristics of the Comparator/DAC
      3. 6.9.3  Detailed Descriptions
      4. 6.9.4  Serial Peripheral Interface (SPI) Module
        1. 6.9.4.1 SPI Master Mode Electrical Data/Timing
          1. Table 6-37 SPI Master Mode External Timing (Clock Phase = 0)
          2. Table 6-38 SPI Master Mode External Timing (Clock Phase = 1)
        2. 6.9.4.2 SPI Slave Mode Electrical Data/Timing
          1. Table 6-39 SPI Slave Mode External Timing (Clock Phase = 0)
          2. Table 6-40 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 6.9.5  Serial Communications Interface (SCI) Module
      6. 6.9.6  Local Interconnect Network (LIN)
      7. 6.9.7  Enhanced Controller Area Network (eCAN) Module
      8. 6.9.8  Inter-Integrated Circuit (I2C)
        1. 6.9.8.1 I2C Electrical Data/Timing
          1. Table 6-46 I2C Timing Requirements
          2. Table 6-47 I2C Switching Characteristics
      9. 6.9.9  Enhanced PWM Modules (ePWM1/2/3/4/5/6/7)
        1. 6.9.9.1 ePWM Electrical Data/Timing
          1. Table 6-50 ePWM Timing Requirements
          2. Table 6-51 ePWM Switching Characteristics
        2. 6.9.9.2 Trip-Zone Input Timing
          1. Table 6-52 Trip-Zone Input Timing Requirements
      10. 6.9.10 High-Resolution PWM (HRPWM)
        1. 6.9.10.1 HRPWM Electrical Data/Timing
          1. Table 6-53 High-Resolution PWM Characteristics
      11. 6.9.11 Enhanced Capture Module (eCAP1)
        1. 6.9.11.1 eCAP Electrical Data/Timing
          1. Table 6-55 Enhanced Capture (eCAP) Timing Requirement
          2. Table 6-56 eCAP Switching Characteristics
      12. 6.9.12 High-Resolution Capture (HRCAP) Module
        1. 6.9.12.1 HRCAP Electrical Data/Timing
          1. Table 6-58 High-Resolution Capture (HRCAP) Timing Requirements
      13. 6.9.13 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.9.13.1 eQEP Electrical Data/Timing
          1. Table 6-60 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
          2. Table 6-61 eQEP Switching Characteristics
      14. 6.9.14 JTAG Port
      15. 6.9.15 General-Purpose Input/Output (GPIO) MUX
        1. 6.9.15.1 GPIO Electrical Data/Timing
          1. 6.9.15.1.1 GPIO - Output Timing
            1. Table 6-67 General-Purpose Output Switching Characteristics
          2. 6.9.15.1.2 GPIO - Input Timing
            1. Table 6-68 General-Purpose Input Timing Requirements
          3. 6.9.15.1.3 Sampling Window Width for Input Signals
          4. 6.9.15.1.4 Low-Power Mode Wakeup Timing
            1. Table 6-69 IDLE Mode Timing Requirements
            2. Table 6-70 IDLE Mode Switching Characteristics
            3. Table 6-71 STANDBY Mode Timing Requirements
            4. Table 6-72 STANDBY Mode Switching Characteristics
            5. Table 6-73 HALT Mode Timing Requirements
            6. Table 6-74 HALT Mode Switching Characteristics
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Design or Reference Design
  8. 8器件和文档支持
    1. 8.1 使用入门
    2. 8.2 器件和开发支持工具命名规则
    3. 8.3 工具与软件
    4. 8.4 文档支持
    5. 8.5 相关链接
    6. 8.6 Community Resources
    7. 8.7 商标
    8. 8.8 静电放电警告
    9. 8.9 Glossary
  9. 9机械、封装和可订购信息
    1. 9.1 封装信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Local Interconnect Network (LIN)

The device contains one LIN controller. The LIN standard is based on the SCI (UART) serial data link format. The LIN module can be configured to work as a SCI as well.

The LIN module has the following features:

  • Compatible to LIN 1.3 or 2.0 protocols
  • Two external pins: LINRX and LINTX
  • Multibuffered receive and transmit units
  • Identification masks for message filtering
  • Automatic master header generation
    • Programmable sync break field
    • Sync field
    • Identifier field
  • Slave automatic synchronization
    • Sync break detection
    • Optional baudrate update
    • Synchronization validation
  • 231 programmable transmission rates with 7 fractional bits
  • Wakeup on LINRX dominant level from transceiver
  • Automatic wakeup support
    • Wakeup signal generation
    • Expiration times on wakeup signals
  • Automatic bus idle detection
  • Error detection
    • Bit error
    • Bus error
    • No-response error
    • Checksum error
    • Sync field error
    • Parity error
  • 2 Interrupt lines with priority encoding for:
    • Receive
    • Transmit
    • ID, error and status

NOTE

The 2803x devices have passed LIN 2.0 conformance tests (master and slave). Contact TI for details.

For more information on the LIN, see the Local Interconnect Network (LIN) Module chapter in the TMS320F2803x Piccolo Technical Reference Manual.

The registers in Table 6-42 configure and control the operation of the LIN module.

Table 6-42 LIN-A Registers(1)

NAME ADDRESS SIZE (x16) DESCRIPTION
SCIGCR0 0x6C00 2 Global Control Register 0
SCIGCR1 0x6C02 2 Global Control Register 1
SCIGCR2 0x6C04 2 Global Control Register 2
SCISETINT 0x6C06 2 Interrupt Enable Register
SCICLEARINT 0x6C08 2 Interrupt Disable Register
SCISETINTLVL 0x6C0A 2 Set Interrupt Level Register
SCICLEARINTLVL 0x6C0C 2 Clear Interrupt Level Register
SCIFLR 0x6C0E 2 Flag Register
SCIINTVECT0 0x6C10 2 Interrupt Vector Offset Register 0
SCIINTVECT1 0x6C12 2 Interrupt Vector Offset Register 1
SCIFORMAT 0x6C14 2 Length Control register
BRSR 0x6C16 2 Baud Rate Selection Register
SCIED 0x6C18 2 Emulation buffer register
SCIRD 0x6C1A 2 Receiver data buffer register
SCITD 0x6C1C 2 Transmit data buffer register
Reserved 0x6C1E 4 RSVD
SIPIO2 0x6C22 2 Pin control register 2
Reserved 0x6C24 10 RSVD
LINCOMP 0x6C30 2 Compare register
LINRD0 0x6C32 2 Receive data register 0
LINRD1 0x6C34 2 Receive data register 1
LINMASK 0x6C36 2 Acceptance mask register
LINID 0x6C38 2 Register containing ID- byte, ID-SlaveTask byte, and ID received fields.
LINTD0 0x6C3A 2 Transmit Data Register 0
LINTD1 0x6C3C 2 Transmit Data Register 1
MBRSR 0x6C3E 2 Baud Rate Selection Register
Reserved 0x6C40 8 RSVD
IODFTCTRL 0x6C48 2 IODFT for BLIN
Some registers and some bits in other registers are EALLOW-protected. For more details, see the Local Interconnect Network (LIN) Module chapter in the TMS320F2803x Piccolo Technical Reference Manual.

Figure 6-34 shows the LIN module block diagram.

TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034 TMS320F28035 lin_block_prs584.gifFigure 6-34 LIN Block Diagram