ZHCSA13M November   2008  – January 2019 TMS320F28020 , TMS320F280200 , TMS320F28021 , TMS320F28022 , TMS320F28023 , TMS320F28026 , TMS320F28027

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Automotive
    3. 5.3  ESD Ratings – Commercial
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 TMS320F2802x/F280200 Current Consumption at 40-MHz SYSCLKOUT
      2. Table 5-2 TMS320F2802x Current Consumption at 50-MHz SYSCLKOUT
      3. Table 5-3 TMS320F2802x Current Consumption at 60-MHz SYSCLKOUT
      4. 5.5.1     Reducing Current Consumption
      5. 5.5.2     Current Consumption Graphs (VREG Enabled)
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics
      1. 5.7.1 PT Package
      2. 5.7.2 DA Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  Emulator Connection Without Signal Buffering for the MCU
    10. 5.10 Parameter Information
      1. 5.10.1 Timing Parameter Symbology
      2. 5.10.2 General Notes on Timing Parameters
    11. 5.11 Test Load Circuit
    12. 5.12 Power Sequencing
      1. Table 5-5 Reset (XRS) Timing Requirements
      2. Table 5-6 Reset (XRS) Switching Characteristics
    13. 5.13 Clock Specifications
      1. 5.13.1 Device Clock Table
        1. Table 5-7  2802x Clock Table and Nomenclature (40-MHz Devices)
        2. Table 5-8  2802x Clock Table and Nomenclature (50-MHz Devices)
        3. Table 5-9  2802x Clock Table and Nomenclature (60-MHz Devices)
        4. Table 5-10 Device Clocking Requirements/Characteristics
        5. Table 5-11 Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics
      2. 5.13.2 Clock Requirements and Characteristics
        1. Table 5-12 XCLKIN Timing Requirements – PLL Enabled
        2. Table 5-13 XCLKIN Timing Requirements – PLL Disabled
        3. Table 5-14 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
    14. 5.14 Flash Timing
      1. Table 5-15 Flash/OTP Endurance for T Temperature Material
      2. Table 5-16 Flash/OTP Endurance for S Temperature Material
      3. Table 5-17 Flash/OTP Endurance for Q Temperature Material
      4. Table 5-18 Flash Parameters at 60-MHz SYSCLKOUT
      5. Table 5-19 Flash Parameters at 50-MHz SYSCLKOUT
      6. Table 5-20 Flash Parameters at 40-MHz SYSCLKOUT
      7. Table 5-21 Flash Program/Erase Time
      8. Table 5-22 Flash/OTP Access Timing
      9. Table 5-23 Flash Data Retention Duration
  6. 6Detailed Description
    1. 6.1 Overview
      1. 6.1.1  CPU
      2. 6.1.2  Memory Bus (Harvard Bus Architecture)
      3. 6.1.3  Peripheral Bus
      4. 6.1.4  Real-Time JTAG and Analysis
      5. 6.1.5  Flash
      6. 6.1.6  M0, M1 SARAMs
      7. 6.1.7  L0 SARAM
      8. 6.1.8  Boot ROM
        1. 6.1.8.1 Emulation Boot
        2. 6.1.8.2 GetMode
        3. 6.1.8.3 Peripheral Pins Used by the Bootloader
      9. 6.1.9  Security
      10. 6.1.10 Peripheral Interrupt Expansion (PIE) Block
      11. 6.1.11 External Interrupts (XINT1–XINT3)
      12. 6.1.12 Internal Zero Pin Oscillators, Oscillator, and PLL
      13. 6.1.13 Watchdog
      14. 6.1.14 Peripheral Clocking
      15. 6.1.15 Low-power Modes
      16. 6.1.16 Peripheral Frames 0, 1, 2 (PFn)
      17. 6.1.17 General-Purpose Input/Output (GPIO) Multiplexer
      18. 6.1.18 32-Bit CPU-Timers (0, 1, 2)
      19. 6.1.19 Control Peripherals
      20. 6.1.20 Serial Port Peripherals
    2. 6.2 Memory Maps
    3. 6.3 Register Maps
    4. 6.4 Device Emulation Registers
    5. 6.5 VREG/BOR/POR
      1. 6.5.1 On-chip Voltage Regulator (VREG)
        1. 6.5.1.1 Using the On-chip VREG
        2. 6.5.1.2 Disabling the On-chip VREG
      2. 6.5.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit
    6. 6.6 System Control
      1. 6.6.1 Internal Zero Pin Oscillators
      2. 6.6.2 Crystal Oscillator Option
      3. 6.6.3 PLL-Based Clock Module
      4. 6.6.4 Loss of Input Clock (NMI Watchdog Function)
      5. 6.6.5 CPU-Watchdog Module
    7. 6.7 Low-power Modes Block
    8. 6.8 Interrupts
      1. 6.8.1 External Interrupts
        1. 6.8.1.1 External Interrupt Electrical Data/Timing
          1. Table 6-21 External Interrupt Timing Requirements
          2. Table 6-22 External Interrupt Switching Characteristics
    9. 6.9 Peripherals
      1. 6.9.1  Analog Block
        1. 6.9.1.1 Analog-to-Digital Converter (ADC)
          1. 6.9.1.1.1 Features
          2. 6.9.1.1.2 ADC Start-of-Conversion Electrical Data/Timing
            1. Table 6-25 External ADC Start-of-Conversion Switching Characteristics
          3. 6.9.1.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
            1. Table 6-26  ADC Electrical Characteristics
            2. Table 6-27  ADC Power Modes
            3. 6.9.1.1.3.1 Internal Temperature Sensor
              1. Table 6-28 Temperature Sensor Coefficient
            4. 6.9.1.1.3.2 ADC Power-Up Control Bit Timing
              1. Table 6-29 ADC Power-Up Delays
            5. 6.9.1.1.3.3 ADC Sequential and Simultaneous Timings
        2. 6.9.1.2 ADC MUX
        3. 6.9.1.3 Comparator Block
          1. 6.9.1.3.1 On-Chip Comparator/DAC Electrical Data/Timing
            1. Table 6-31 Electrical Characteristics of the Comparator/DAC
      2. 6.9.2  Detailed Descriptions
      3. 6.9.3  Serial Peripheral Interface (SPI) Module
        1. 6.9.3.1 SPI Master Mode Electrical Data/Timing
          1. Table 6-33 SPI Master Mode External Timing (Clock Phase = 0)
          2. Table 6-34 SPI Master Mode External Timing (Clock Phase = 1)
        2. 6.9.3.2 SPI Slave Mode Electrical Data/Timing
          1. Table 6-35 SPI Slave Mode External Timing (Clock Phase = 0)
          2. Table 6-36 SPI Slave Mode External Timing (Clock Phase = 1)
      4. 6.9.4  Serial Communications Interface (SCI) Module
      5. 6.9.5  Inter-Integrated Circuit (I2C)
        1. 6.9.5.1 I2C Electrical Data/Timing
          1. Table 6-39 I2C Timing Requirements
          2. Table 6-40 I2C Switching Characteristics
      6. 6.9.6  Enhanced PWM Modules (ePWM1/2/3/4)
        1. 6.9.6.1 ePWM Electrical Data/Timing
          1. Table 6-42 ePWM Timing Requirements
          2. Table 6-43 ePWM Switching Characteristics
        2. 6.9.6.2 Trip-Zone Input Timing
          1. Table 6-44 Trip-Zone Input Timing Requirements
      7. 6.9.7  High-Resolution PWM (HRPWM)
        1. 6.9.7.1 HRPWM Electrical Data/Timing
          1. Table 6-45 High-Resolution PWM Characteristics at SYSCLKOUT = 50 MHz–60 MHz
      8. 6.9.8  Enhanced Capture Module (eCAP1)
        1. 6.9.8.1 eCAP Electrical Data/Timing
          1. Table 6-47 Enhanced Capture (eCAP) Timing Requirement
          2. Table 6-48 eCAP Switching Characteristics
      9. 6.9.9  JTAG Port
      10. 6.9.10 General-Purpose Input/Output (GPIO) MUX
        1. 6.9.10.1 GPIO Electrical Data/Timing
          1. 6.9.10.1.1 GPIO - Output Timing
            1. Table 6-54 General-Purpose Output Switching Characteristics
          2. 6.9.10.1.2 GPIO - Input Timing
            1. Table 6-55 General-Purpose Input Timing Requirements
          3. 6.9.10.1.3 Sampling Window Width for Input Signals
          4. 6.9.10.1.4 Low-Power Mode Wakeup Timing
            1. Table 6-56 IDLE Mode Timing Requirements
            2. Table 6-57 IDLE Mode Switching Characteristics
            3. Table 6-58 STANDBY Mode Timing Requirements
            4. Table 6-59 STANDBY Mode Switching Characteristics
            5. Table 6-60 HALT Mode Timing Requirements
            6. Table 6-61 HALT Mode Switching Characteristics
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Design or Reference Design
  8. 8器件和文档支持
    1. 8.1 使用入门
    2. 8.2 器件和开发支持工具命名规则
    3. 8.3 工具与软件
    4. 8.4 文档支持
    5. 8.5 相关链接
    6. 8.6 Community Resources
    7. 8.7 商标
    8. 8.8 静电放电警告
    9. 8.9 Glossary
  9. 9机械、封装和可订购信息
    1. 9.1 封装信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Enhanced PWM Modules (ePWM1/2/3/4)

The devices contain up to four enhanced PWM Modules (ePWM). Figure 6-35 shows a block diagram of multiple ePWM modules. Figure 6-36 shows the signal interconnections with the ePWM. For more details, see the Enhanced Pulse Width Modulator (ePWM) chapter in the TMS320F2802x,TMS320F2802xx Piccolo Technical Reference Manual.

Table 6-41shows the complete ePWM register set per module.

TMS320F28027 TMS320F28026 TMS320F28023 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200 epwm_prs523.gifFigure 6-35 ePWM

Table 6-41 ePWM Control and Status Registers

NAME ePWM1 ePWM2 ePWM3 ePWM4 SIZE (x16) / #SHADOW DESCRIPTION
TBCTL 0x6800 0x6840 0x6880 0x68C0 1 / 0 Time Base Control Register
TBSTS 0x6801 0x6841 0x6881 0x68C1 1 / 0 Time Base Status Register
TBPHSHR 0x6802 0x6842 0x6882 0x68C2 1 / 0 Time Base Phase HRPWM Register
TBPHS 0x6803 0x6843 0x6883 0x68C3 1 / 0 Time Base Phase Register
TBCTR 0x6804 0x6844 0x6884 0x68C4 1 / 0 Time Base Counter Register
TBPRD 0x6805 0x6845 0x6885 0x68C5 1 / 1 Time Base Period Register Set
TBPRDHR 0x6806 0x6846 0x6886 0x68C6 1 / 1 Time Base Period High Resolution Register(1)
CMPCTL 0x6807 0x6847 0x6887 0x68C7 1 / 0 Counter Compare Control Register
CMPAHR 0x6808 0x6848 0x6888 0x68C8 1 / 1 Time Base Compare A HRPWM Register
CMPA 0x6809 0x6849 0x6889 0x68C9 1 / 1 Counter Compare A Register Set
CMPB 0x680A 0x684A 0x688A 0x68CA 1 / 1 Counter Compare B Register Set
AQCTLA 0x680B 0x684B 0x688B 0x68CB 1 / 0 Action Qualifier Control Register For Output A
AQCTLB 0x680C 0x684C 0x688C 0x68CC 1 / 0 Action Qualifier Control Register For Output B
AQSFRC 0x680D 0x684D 0x688D 0x68CD 1 / 0 Action Qualifier Software Force Register
AQCSFRC 0x680E 0x684E 0x688E 0x68CE 1 / 1 Action Qualifier Continuous S/W Force Register Set
DBCTL 0x680F 0x684F 0x688F 0x68CF 1 / 1 Dead-Band Generator Control Register
DBRED 0x6810 0x6850 0x6890 0x68D0 1 / 0 Dead-Band Generator Rising Edge Delay Count Register
DBFED 0x6811 0x6851 0x6891 0x68D1 1 / 0 Dead-Band Generator Falling Edge Delay Count Register
TZSEL 0x6812 0x6852 0x6892 0x68D2 1 / 0 Trip Zone Select Register(1)
TZDCSEL 0x6813 0x6853 0x6893 0x98D3 1 / 0 Trip Zone Digital Compare Register
TZCTL 0x6814 0x6854 0x6894 0x68D4 1 / 0 Trip Zone Control Register(1)
TZEINT 0x6815 0x6855 0x6895 0x68D5 1 / 0 Trip Zone Enable Interrupt Register(1)
TZFLG 0x6816 0x6856 0x6896 0x68D6 1 / 0 Trip Zone Flag Register (1)
TZCLR 0x6817 0x6857 0x6897 0x68D7 1 / 0 Trip Zone Clear Register(1)
TZFRC 0x6818 0x6858 0x6898 0x68D8 1 / 0 Trip Zone Force Register(1)
ETSEL 0x6819 0x6859 0x6899 0x68D9 1 / 0 Event Trigger Selection Register
ETPS 0x681A 0x685A 0x689A 0x68DA 1 / 0 Event Trigger Prescale Register
ETFLG 0x681B 0x685B 0x689B 0x68DB 1 / 0 Event Trigger Flag Register
ETCLR 0x681C 0x685C 0x689C 0x68DC 1 / 0 Event Trigger Clear Register
ETFRC 0x681D 0x685D 0x689D 0x68DD 1 / 0 Event Trigger Force Register
PCCTL 0x681E 0x685E 0x689E 0x68DE 1 / 0 PWM Chopper Control Register
HRCNFG 0x6820 0x6860 0x68A0 0x68E0 1 / 0 HRPWM Configuration Register(1)
HRPWR 0x6821 - - - 1 / 0 HRPWM Power Register
HRMSTEP 0x6826 - - - 1 / 0 HRPWM MEP Step Register
HRPCTL 0x6828 0x6868 0x68A8 0x68E8 1 / 0 High resolution Period Control Register(1)
TBPRDHRM 0x682A 0x686A 0x68AA 0x68EA 1 / W(2) Time Base Period HRPWM Register Mirror
TBPRDM 0x682B 0x686B 0x68AB 0x68EB 1 / W(2) Time Base Period Register Mirror
CMPAHRM 0x682C 0x686C 0x68AC 0x68EC 1 / W(2) Compare A HRPWM Register Mirror
CMPAM 0x682D 0x686D 0x68AD 0x68ED 1 / W(2) Compare A Register Mirror
DCTRIPSEL 0x6830 0x6870 0x68B0 0x68F0 1 / 0 Digital Compare Trip Select Register (1)
DCACTL 0x6831 0x6871 0x68B1 0x68F1 1 / 0 Digital Compare A Control Register(1)
DCBCTL 0x6832 0x6872 0x68B2 0x68F2 1 / 0 Digital Compare B Control Register(1)
DCFCTL 0x6833 0x6873 0x68B3 0x68F3 1 / 0 Digital Compare Filter Control Register(1)
DCCAPCT 0x6834 0x6874 0x68B4 0x68F4 1 / 0 Digital Compare Capture Control Register(1)
DCFOFFSET 0x6835 0x6875 0x68B5 0x68F5 1 / 1 Digital Compare Filter Offset Register
DCFOFFSETCNT 0x6836 0x6876 0x68B6 0x68F6 1 / 0 Digital Compare Filter Offset Counter Register
DCFWINDOW 0x6837 0x6877 0x68B7 0x68F7 1 / 0 Digital Compare Filter Window Register
DCFWINDOWCNT 0x6838 0x6878 0x68B8 0x68F8 1 / 0 Digital Compare Filter Window Counter Register
DCCAP 0x6839 0x6879 0x68B9 0x68F9 1 / 1 Digital Compare Counter Capture Register
Registers that are EALLOW protected.
W = Write to shadow register
TMS320F28027 TMS320F28026 TMS320F28023 TMS320F28022 TMS320F28021 TMS320F28020 TMS320F280200 fbd_hires_prs523.gif
These events are generated by the Type 1 ePWM digital compare (DC) submodule based on the levels of the COMPxOUT and TZ signals.
Figure 6-36 ePWM Submodules Showing Critical Internal Signal Interconnections