ZHCSJM2A April   2019  – May 2019 TMP235-Q1 , TMP236-Q1

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      功能方框图
      2.      输出电压与环境温度间的关系
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Connection to an ADC
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11器件和文档支持
    1. 11.1 相关链接
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Thermal Information

THERMAL METRIC (1)(2) TMP23X-Q1 UNIT
DCK (SC70) DBZ (SOT-23)
PINS PINS
RθJA Junction-to-ambient thermal resistance(3)(4) 275 167 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 84 90 °C/W
RθJB Junction-to-board thermal resistance 56 146 °C/W
ΨJT Junction-to-top characterization parameter 1.2 35 °C/W
ΨJB Junction-to-board characterization parameter 55 146 °C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
For information on self-heating and thermal response time seeLayout Guidelinessection.
The junction to ambient thermal resistance (RθJA ) under natural convection is obtained in a simulation on a JEDEC-standard, High-K board as specified in JESD51-7, in an environment described in JESD51-2. Exposed pad packages assume that thermal vias are included in the PCB, per JESD 51-5.
Changes in output due to self heating can be computed by multiplying the internal dissipation by the thermal resistance.